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Re: TF1230 Beta Interest (Open Source)

Posted: 21 Aug 2021 21:21
by go0se
No timing fixes have been applied to any of them. I will read up on what is needed, do the modifications as required for each revision and test again.

Cheers.

Re: TF1230 Beta Interest (Open Source)

Posted: 21 Aug 2021 21:29
by terriblefire
A note.... timing fixes correct overvoltage spikes on the clock line.

Its one thing to say "my accelerator doesnt need the fixes because its well made"... but realize that a 6-7V peak to peak spike on the clock line is not going to be doing your chipset any good in the long term.

The timing fix isnt something you need to do because accelerators have fussy knickers. Its a manufacturer recommended action. Its as important if not more important than recapping.

Re: TF1230 Beta Interest (Open Source)

Posted: 21 Aug 2021 21:31
by supaduper
Goose 99% of the time just removing E123C, E125C will do the trick regarding the timing fix

Re: TF1230 Beta Interest (Open Source)

Posted: 21 Aug 2021 22:17
by go0se
Cheers guys,

I've just tried the cap removal on the 1A and 1D4 boards but without success. Looks like further study of the http://ianstedman.co.uk/amiga-related/a ... ard-fixes/ page and trying some more of those possible combinations will be necessary. I'll get onto it tomorrow.

Re: TF1230 Beta Interest (Open Source)

Posted: 22 Aug 2021 00:50
by alenppc
go0se wrote: 21 Aug 2021 22:17 Cheers guys,

I've just tried the cap removal on the 1A and 1D4 boards but without success. Looks like further study of the http://ianstedman.co.uk/amiga-related/a ... ard-fixes/ page and trying some more of those possible combinations will be necessary. I'll get onto it tomorrow.
Looks like you stumbled upon the same issue that happens on my A1200s (both Rev 1d.4), they just give me a yellow screen with the 1230 (this is not related to timing fixes since they are already done on my boards). Further testing will happen on Monday...

Re: TF1230 Beta Interest (Open Source)

Posted: 22 Aug 2021 07:48
by go0se
@alenppc The yellow/mustard screen on the 1D4 remains constant on some boot cycles but on other occasions gives way to a repeating black screen loop of jet black then dark grey similar to the screen pattern on the CD32 at power on with the TF330 installed, but on a loop. The behaviour is the same for both cards - Both cards boot and test ok on the 2B.

@terriblefire I have a logic adapter here for the 1200, are there any signals that I can probe during this boot loop that would be of any help? Also anything I could try in Diagrom ?


DSC_1694.resized.JPG

Re: TF1230 Beta Interest (Open Source)

Posted: 22 Aug 2021 14:14
by terriblefire
Does Diagrom boot? If not then its 100% clock line related somehow.

Re: TF1230 Beta Interest (Open Source)

Posted: 22 Aug 2021 15:03
by go0se
Boots to Diagrom on the 1A machine, which doesn't boot with standard roms. That's the only machine I've tested with DR so far, I need to burn another set of Daigroms as these ones are on their last legs (pun intended)

No issues that I can see with the diagrom POST. 030 and 64MB fast detected.

Manual memory test bombs out with an "illegal instruction detected" dump about 2MB into running the test. rather than a memory failure error. See image below.

ManMemDump.PNG

Re: TF1230 Beta Interest (Open Source)

Posted: 22 Aug 2021 15:55
by alenppc
go0se wrote: 22 Aug 2021 15:03 Boots to Diagrom on the 1A machine, which doesn't boot with standard roms. That's the only machine I've tested with DR so far, I need to burn another set of Daigroms as these ones are on their last legs (pun intended)

No issues that I can see with the diagrom POST. 030 and 64MB fast detected.

Manual memory test bombs out with an "illegal instruction detected" dump about 2MB into running the test. rather than a memory failure error. See image below.


ManMemDump.PNG
I can 100% reproduce this exactly.

Re: TF1230 Beta Interest (Open Source)

Posted: 22 Aug 2021 20:22
by terriblefire
I just need to reproduce it here. My Rev 1 A1200 is not booting with or without a card.