coonsgm wrote: 28 Nov 2025 22:21
Perfect! All set to make the changes tomorrow.
Hopefully it will be a win... We definitely need more wins! :lol:
Re: REV 3 - REV 5 - The beginning (ST536)
Posted: 28 Nov 2025 23:15
by exxos
If it helps anyone.. This is how I solder the PLD...
Re: REV 3 - REV 5 - The beginning (ST536)
Posted: 29 Nov 2025 17:26
by coonsgm
Ok first bottom of the board changes and the PLD are done.
Now I have one more question. The SDRAM modification, does it need to be done to both SDRAM IC's?
Re: REV 3 - REV 5 - The beginning (ST536)
Posted: 29 Nov 2025 17:34
by coonsgm
It looks like my board is an earlier version with some minor changes, but I'm also having a harder time finding which line is to be connected to the SDRAM.
IMG_3894.jpeg
IMG_3893.jpeg
Re: REV 3 - REV 5 - The beginning (ST536)
Posted: 29 Nov 2025 18:06
by exxos
coonsgm wrote: 29 Nov 2025 17:34
It looks like my board is an earlier version with some minor changes, but I'm also having a harder time finding which line is to be connected to the SDRAM.
Which end? You can count the pins on the SDRAM and PLD to see where the wire goes..
The PLD tracks are pointing towards the "50MHz" text..
Re: REV 3 - REV 5 - The beginning (ST536)
Posted: 29 Nov 2025 19:07
by coonsgm
Could you share a zoomed out photo of the entire board top and bottom? I can't tell from the current photo which corner of the PLD you're looking at.
Thanks!
Re: REV 3 - REV 5 - The beginning (ST536)
Posted: 29 Nov 2025 19:11
by exxos
coonsgm wrote: 29 Nov 2025 19:07
Could you share a zoomed out photo of the entire board top and bottom? I can't tell from the current photo which corner of the PLD you're looking at.
I can but I'm not at home until Tuesday now..
Re: REV 3 - REV 5 - The beginning (ST536)
Posted: 29 Nov 2025 19:26
by coonsgm
No worries :)
Re: REV 3 - REV 5 - The beginning (ST536)
Posted: 29 Nov 2025 22:44
by coonsgm
Alright,
I made all the changes:
I connected the 5th pin on the PLD to the 10th pin on the closest SDRAM IC
IMG_3903.jpeg
IMG_3906.jpeg
Added the 330R to the two pins on the CPU
Connected the two capacitors on the backside
Doubled up all the small birdseed capacitors with 4.7nf's added (dang those are small)
IMG_3904.jpeg
IMG_3905.jpeg
Programmed the PLD with BETA1SS.jed (photo is an in-process, but it did complete and verify)
IMG_3898.jpeg
It looks like the FastRam is having issues...I've used this ROM before with the 144 and it was mostly stable with FastRam working.
IMG_3901.jpeg
IMG_3900.jpeg
Ran Gembench, just because (IDE working just fine)
IMG_3902.jpeg
I'm sure I did something wrong here, so any feedback is much appreciated!