exxos's Atari, Amiga & retro forum

Stimpy wrote: 25 Oct 2018 20:29 The 5v you see on the pin is probably just leakage current and the tiny ESD diodes inside the FPGA will just clamp that, it'll be microamps.

I am using a meter, and even tried 1 meg load and still firm 5V. The datasheet hints at 1K being needed.

The only other way it could possibly work is it normal 5V tolerant bus transceivers are used, and the FPGA code had a output disable the buffers.. This is what I was trying to explain to Wolfgang..

Unfortunately I know absolutely nothing about FPGA coding. I only thing I have available is the code as is, which I've converted to a schematic symbol where I should be able to link up to actual pins. But even that I am not really sure about how it all works. But I have used the software briefly so I think I can do it.

So this is all based on assumptions that I'm going to have to solve this problem myself on a logic level which basically means I cannot use normal bus transceivers.

EDIT:
Actually no, I don't think that would work, CPU would need to access the blitter I think anyway.. I think I had this conversation before possibly with Rodolphe... I think it was the FPGA still read from the ports even when tri-stated... This would not really be possible with external buffers, I don't think so anyway.. As once they are tri-stated, the FPGA would no longer be able to access the bus...

EDIT2:
Possible if the buffers were set to READ direction when the FPGA went tri-stated... That would probably emulate it all.. But it was still need a redesign my board with a chip with direction control, which these IDT chips don't have anyway..

Assuming it will be possible to do that with a direction control pin. It would still need modifications to into the core which I cannot do anyway. But I think rather than just starting messing about with code making changes, I really want to just stick to Wolfgang's original code without having to make changes, because if anything gets updated, I won't be easy to update cores on my board... Without changes being made again, and even if someone else does changes, they might not be around the years time or maybe too busy to do the changes..

So I think just going with a simple logic level interface using resistors and diodes arrangement would be a better idea long term.

I haven't looked at the code but I assume there is one variable that is used to tri-state the bus. If there is any extra pin available on the FPGA, route that signal to a pin and use it to enable/disable the external buffer the same way the pin are tri-stated in the FPGA.
You can then use bidirectional buffer (like the LVC series) for the data and address.
IF not we can probably use the BG/BGACK and R/W signals (and may be others) to set the direction on the buffers when the blitter is bus master or accessed by the CPU to read/write its registers.

rpineau wrote: 25 Oct 2018 21:09 I haven looked at the code but I assume there is one variable that is used to tri-state the bus. If there is any extra pin available on the FPGA, route that signal to a pin and use it to enable/disable the external buffer the same way the pin are tri-stated in the FPGA.
You can then use bidirectional buffer (like the LVC series) for the data and address.
IF not we can probably use the BG/BGACK and R/W signals (and may be others) to set the direction on the buffers when the blitter is bus master or accessed by the CPU to read/write its registers.

That may work as said above, but I am not sure if blitter reads the bus when tristated... and still would need code changes which I Cannot do.

I don't think we need code changes.
We need to use external known signals from outside the blitter the manage the direction of the buffer:
Blitter is not bus master :
ST Address -> Blitter
ST data bi-directional when accessing the blitter based on R/W and blitter DTACK (and may be other signals .. I haven't thought that one through).

Blitter is bus master :
Blitter Address -> St Address bus
Blitter data bi-directional , use blitter R/W to drive the buffer direction.

We should even be able to test this with a real blitter and 5V logic.

You mean like use BGACK to enable/disable tri-state buffers or something ? I did wonder that, but wouldn't work if something else is bus master.

As I said .. I didn't do the actual thinking it through :)
But with the blitter BGACK , BGKI and a few other we should be able to built a state table that tells us when the blitter is bus master.
If there is 5V on BGKI, and 0V on BGACK .. blitter is the bus master.
This is not easy of course as the blitter is basically like a 2nd CPU as it can be bus master and do read/write to the whole memory space.
But if we can get it working with buffers on a real 5V blitter then we can get it working with the FPGA with no code changes

Yeah tricky... but using resistor divider type stuff, just don't have to bother with anything I think. Pretty much wire it in and done. No need for IC's or direction control or isolation or interfaces or code changes..

EDIT:

Need to look at this when more awake :roll: The way I was thinking is tricky because both sides need to pull down the bus, but also isolate 5V & 3.3V... So its back to the IDT buffer as such bi-directional needs something more like a mosfet :roll: So might just be easier to remove the 3.3V regulator off this board, (have to go elsewhere, stacked pcb or something) and use some tiny resistor packs for pull ups...

Actually same as this as mentioned ages ago.. but this actually mentions it works with open collector...

http://www.hobbytronics.co.uk/mosfet-vo ... -converter

I have gone back to the IDT chip to do more tests with pull-ups on the 3.3V side...

Chip is powered from 5V, via a diode (as suggested in the document ) which gives 4.2V actual chip VCC.


1.1K pull-up, I get 3.85V
2.2K pull-up, I get 4.13 V.
10K pull-up, I get 4.65 V.

I also tried some pull downs..
10K pull-down, I get 4.06V.
1.1K pull-down, I get 1.66V.


There is a chart which mentions resistor values, it does not seem to actually mention is relevant to :roll: It does seem as they mention though, the higher the load, the higher the voltage drop.. But this still does not seem to be correct as I should be seeing 3.3V on the output surely ?!


This is the info about the chip...


Saying A & B are solidly connected, that does seem apparent to me, but also I see 5V input and 5V output..

But then the datasheet then says the output is clamped to 4V ?! Obviously this does not happen as I get 5V! If anything it should be 4.2V as that is what is on VCC of the chip.


Current setup...


So I don't think the resistors are actually the solution here.. This just seems to be loading the to the point that the voltage drops..

The chip itself should inherently somehow limit the output voltage, but even so, 4V is still to high for 3.3V work.

So I think I am going to see if I can find some other chip which is equivalent to this one and see if there some better information on it...

Also going to run some more simulations on the MOSFET version...

EDIT:

Here it is... working fine ?!



To be continued....

I give up, I have ordered one of these boards..

http://www.hobbytronics.co.uk/logic-lev ... r-4channel


This pretty much matches my simulation model. I have messed around with the simulation loads and it just simply works perfectly. So this board should allow me to actually test it on the real circuit.

I have also been looking at other chips and this texas part looks interesting...
http://www.ti.com/product/txb0108

Only 8bit, more along the lines of a proper voltage translator buffer.. But no direction pin that is what I am looking for.. And this should work fine for tri-state circuits as well that having to mess about..

It looks like a demo board exist.. So will see if I can obtain one of these...

https://www.mouser.co.uk/ProductDetail/ ... fB%2fRU%3d

EDIT:

8bit demo board ordered :)

Also seen these..
http://www.ti.com/product/sn74cb3t16210 ... Everything

They only seem to do 8bit and 20bit though :roll: Pretty much should be like the IDT chip...