exxos's Atari, Amiga & retro forum

foft wrote: 09 Oct 2022 21:41 I was also wondering, there is no public CPLD HDL for these right?

Somebody correct me if I’m wrong but AFAIK no, there are no public HDL source code for the CPLD. I guess Rodolphe only licensed the bitstreams.

exxos wrote: 09 Oct 2022 22:03

foft wrote: 09 Oct 2022 21:58 You’d think, though… in this case it seems like even with reset low something happens.

In fpga design you don’t need to wire all registers to the reset line. Might be the same with cplds.

Well I think this should be proven first. You could I guess just putting manual toggle switch on the 5V and / or 3.3V line. So you can manually switch one before the other. But don't blame me if you kill the whole thing in doing that :)

So the good news is ...
i) It works!
ii) The falcon still lives!

I cut the ATX 5V lines and put a switch on. When I power on first, then enable 5V it boots every time straight into 060 mode.

Many thanks too @dml for the MOSFET info, now I know it works I'll probably build something like that.

foft wrote: 11 Oct 2022 20:18 So the good news is ...
i) It works!
ii) The falcon still lives!

I cut the ATX 5V lines and put a switch on. When I power on first, then enable 5V it boots every time straight into 060 mode.

Many thanks too @dml for the MOSFET info, now I know it works I'll probably build something like that.

That's very interesting (to me) and a good investigation, foft.

So what's the theory to go along with this empirical evidence, then?

Something driving 5V into the CPLD's GPIO before the 3V3 VCC lines are stable causing a latch up or similar?

Can't quite see what the process would be.

BW

Badwolf wrote: 11 Oct 2022 20:25 So what's the theory to go along with this empirical evidence, then?

Something driving 5V into the CPLD's GPIO before the 3V3 VCC lines are stable causing a latch up or similar?

Erm, good question. I wonder if there is something I can measure to answer this empirically...

Maybe its how the PLD takes control of the bus on power up or something ? Maybe if the CPU powers up first it screws the PLD taking the bus or something :shrug:

I've not investigated yet what is going on, but I did try a few primitive attempts to improve on the manual switch!

I had some relays lying around from a previous project. I tried the one with highest coil resistance (500ohm), but it seems to take too much current to switch on for 'power good' (should only be 10mA, but the voltage dropped significantly). I tried 5v power directly to drive the coil, but it's too soon still (unsurprisingly).

So, plan B. I checked the power supply circuit to see if there is anything trivial I can change. It has this dual buck step-down chip: http://www.anpec.com.tw/ashx_prod_file. ... W7159C.pdf. This explicitly has the soft on 5V ramp up then 3.3v ramp up. The delay can be controlled by SS, which is a current source (30uA) into a capacitor (~120nF). When it hits 1V it starts ramping 5V, then when it hits 1.4V it starts ramping 3.3V. I tried dropping the capacitance a few times, down to the smallest I have here (4.7nF), but it still wasn't enough. It doesn't like a straight short though!

So, onto what I should've done in the first place. Design a circuit with some power mosfets (or easier chips containing them). I started reading the chapter in the Art of Electronics to see what I should know about them.

The circuit posted should do.. But it needs work. It really needs a comparitor set to switch on the bottom mosfet when the voltage reaches 3v.

The bottom MOSFET should be a logic level MOSFET . As 3-5v isn't enough to turn on most MOSFETs properly. Unless you drive from the 12v rail. IIRC most comp chips are open collector. But then needs more work as you need to route the 12v rail as well as the 3.3v and 5v.

Alternative you could use a reset if chip like we used on the H5. Just use a 300ms delay to switch the 5v on.

When the bottom mosfet turns on, it grounds the gate of the P-channel mosfet turning it on. This should be a low RDS on of like 10mR else it will get hot.

EDIT:

There may be mosfet driver chips which may work. Maybe then you could use the 3.3v as a enable signal for the driver chip to switch the top fet.

Recently on atari-forum, user ChainQ (@Chain-Q here ?) explained how he solved the power-up sequence for the NETUSBee using a supervisory circuit MCP10x (for NETUSBee, it required the MCP101). Inspired by his method, I would start with a MCP100 (the active low version) wired to the 3.3v rail. When the MCP100 output is high (3v3 good), it would trigger your relay/mosfet/whatever to allow 5V.

(edit: more precisely, the MCP100-315 that triggers power good between 3v and 3v15)

I was wondering about using the MP5075 (or a few of them), using power good as enable for 5V:
https://www.monolithicpower.com/en/docu ... nt_id/1824

I'll check out the MCP100, thanks @sporniket.

Also, I will probably at least simulate a real mosfet circuit like the one posted!

foft wrote: 15 Oct 2022 07:28 I was wondering about using the MP5075 (or a few of them), using power good as enable for 5V:
https://www.monolithicpower.com/en/docu ... nt_id/1824

I received the MP5075. I didn't design a board yet so I decided to wire it up using a little mini test veroboard thing. Easier said than done given it is only 1.6mm x 1.6mm and has 6 pins! Fortunately two of them are NC. Anyway the circuit is trivial.

Vin -> 5v from ATX supply, also 10uF cap to ground
Vout -> 5v to Falcon ATX input, also 10uF cap to ground
EN -> power good
GND -> ground

Fortunately the chip fits nicely between 4 holes on the veroboard!

Anyway it works perfectly... Boots every time now.

Spot the chip, haha!