So I quickly hooked up my logic analyser to my own good working STE with the original TOS 1.62 ROMs from Bretts machine which are known good.
The LA is connected to the address lines at the ROMs.
This is what I see during startup:
Screenshot 2022-01-25 at 09.59.16.png
So a flat line until power comes on then all lines go to 5v, and we see addresses on the bus and the machine boots.
In contrast, this is Bretts machine, with the same ROMs installed:
Screenshot 2022-01-25 at 10.00.12.png
So everything goes to 5v as expected, but then we don't see any proper address activity on the bus at all, and I am confident that even if I had made some wiring mistakes, or not connected something, I should at least see some bus activity.
Since I have buzzed all the address lines to their next hops on the mainboard, I am confident they should work, and they are all connected socket to socket as per the schematic, I don't believe they can be that far out. I haven't found any shorts either.
Since I know the following all work as tested in my STE:
CPU
RAM
Shifter
I know they aren't the cause. There is a separate Blitter which I can't test in my STE, so I need to find another way to do so.
So I need to start tracking across the address bus and see what's going on. My concern is a problem with the GST MMU/GLUE combo, but more work required.