exxos's Atari, Amiga & retro forum

Yes i broke the 1.04 one. But i have tried with board and without board, both roms the left and both banks of those roms. So far its the same. A question. If there is no correct rom will the screen go black when pressing the reset anyway ?

Here are the current data after i "fixed" the A12 line:

A1-A15

A16-A23

D0-15

With the decoder. The HALT signal does not go LOW. AS gets stuck at 1.4v - 1.5v. And on A1 there is an sinus wave that seems to stretch the future down the addressline i measure. Like A1 has a little bigger sinus wave than A0, A2 a little bigger than A3 etc up to like A6 where i stopped measuring.

Dont know if this is just gibberish or if it give some clue to something.

/zChris

Address lines floating up and down sounds like your pull-ups are not pulling up!

I'm confused what that last scope line is supposed to be, before you stated

Channel 0 at the top is Adressline, Channel 1 is AS and Channel 0 at the bottom is analogue adressline.

So deadliness look fine if they are the top waveform. Same with AS. So I don't know what "analogue adressline" is referring to, I just assume that scope probe was not connected.

In anycase, with all address lines showing zero (can you confirm they are all zero on the ROM also ?) You should have

01100000 00101110

But your data shows
0110000 00000000

It looks like you should check LDS, UDS are both zero when AS is low. High byte looks correct, but lower byte is totally wrong. But even so, LDS,UDS does not effect the ROM as it is driving the bus in 16 bit mode regardless. If anything they should still be correct AFAIK. But worth just double checking LDS,UDS connections from the CPU to GLUE, and check they are all zero after reset also.

But again, the ROM drives the bus, and nothing on the bus can drive it low during ROM access, other than the ROM itself. So if ROM is bad, the data will be wrong. If the address on the ROM is wrong then the data will be wrong. There really is nothing else in the circuit to corrupt the data in such a way. Other than the blitter..

So might be a idea to take out the ROM, and scope out the databus after reset to see if you get all 1's (no need to post scopes of them all) just confirm if they all high without the ROM. If they are not, maybe the bus buffers have failed, or MMU isn't driving them.. but one step at a time..

UDS and LDS are low the first four AS Low but on the fifth AS low UDS and LDS are high, not sure if that has any significance. UDS and LDS also have connection with GLUE.

All the data lanes are 1 when AS are low. There is a difference though between some data lanes. When i hold reset all data lanes EXCEPT 2 , 3, 4 are high. On lane 2 , 3, 4 they are low when i old reset and become high when i release it.

Both these test were done with ROM not in the socket and A12 "patched".

/zChris

exxos wrote: 21 Aug 2021 23:55 I'm confused what that last scope line is supposed to be, before you stated

Channel 0 at the top is Adressline, Channel 1 is AS and Channel 0 at the bottom is analogue adressline.

So deadliness look fine if they are the top waveform. Same with AS. So I don't know what "analogue adressline" is referring to, I just assume that scope probe was not connected.

I believe that "analogue adressline" (with a little 'A0' tag on the left) means the actual voltage of the address line on the probe, and then "channel 0 at the top" (marked 'D0') as well as Channel 1 (marked 'D1') are the interpretations as logic high/low (in other words a logic analyser).

Am I right @zChris ?

sporniket wrote: 22 Aug 2021 07:17]
I believe that "analogue adressline" (with a little 'A0' tag on the left) means the actual voltage of the address line on the probe, and then "channel 0 at the top" (marked 'D0') as well as Channel 1 (marked 'D1') are the interpretations as logic high/low (in other words a logic analyser).

Am I right @zChris ?

But its nowhere near following the top 2 signals.. They are switching fast , that bottom signal is not..

zChris wrote: 22 Aug 2021 02:08 Both these test were done with ROM not in the socket and A12 "patched".

This seems to indicate the ROM IC is bad or the socket isn't contacting to the ROM properly.. There's no other way it can put bad data on the bus other than the address lines are bad to it.