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Re: Suska board
Posted: 20 May 2024 10:19
by Cyprian
if necessary, we can prepare a small AUTO .PRG that will perform a new memory size check and set the OS variables accordingly
Re: Suska board
Posted: 20 May 2024 10:40
by exxos
Cyprian wrote: 20 May 2024 10:19
if necessary, we can prepare a small AUTO .PRG that will perform a new memory size check and set the OS variables accordingly
That would be cool. I never thought of doing that.
Potentially I could build a new build of TOS206 to support it, just I am not familiar with assembly to make those changes.
I guess the problem is there isn't any way of actually testing what TOS does currently. I don't have any simple alt-ram boards to try. Though I guess if alt-ram is enabled on boot, TOS should write a pattern to which could be read back.. Problem being the video will not be accessible. But I don't have time to get sidetracked to another project right now anyway :(
Re: Suska board
Posted: 20 May 2024 10:50
by Cyprian
exxos wrote: 20 May 2024 10:40
Potentially I could build a new build of TOS206 to support it, just I am not familiar with assembly to make those changes.
nice idea, there is a source code for TOS 1.x / 2.x on Thorsten Otto Github, and we could try to extend that memory check.
Also also EmuTOS could handle more ST-RAM memory.
Re: Suska board
Posted: 20 May 2024 10:56
by Cyprian
Re: Suska board
Posted: 20 May 2024 11:26
by exxos
A bit further down the code it does mention ST RAM in the TT..
Code: Select all
/* =========================================================================== */
/* ==== memconf for TT ======================================================= */
/* =========================================================================== */
/*
* The following configurations are valid for ST-RAM in a TT, listed as
* total RAM (motherboard RAM + optional daughterboard RAM):
* 2MB (2MB + 0MB), 4MB (2MB + 2MB), 10MB (2MB + 8MB)
* [According to the TT rev B MCU functional description, it is also
* possible to have 8MB (8MB + 0MB) and 10MB (8MB + 2MB) configurations,
* but I have not seen this.] When an 8MB board is present, it is always
* mapped to the first 8MB of memory.
*
* Systems with only 2MB boards require a memcntlr value of 0x05; systems
* with an 8MB board require a memcntlr value of 0x0a. We detect which
* size of board is in low memory by assuming an 8MB board, then checking
* for different memory addresses mapping to the same physical address.
*
* rfb (sep/2016)
*/
move.w #$0005,d6 /* assume 2MB board */
move.b #$0A,(memconf).w /* set memory controller for 8MB */
moveq.l #0,d0
move.l d0,($00001008).w /* zero out test addresses */
move.l d0,($0000100C).w
move.l #$06161964,d0 /* write test value #1 to an address */
move.l d0,($00000008).w /* that may be mapped into test address #1 */
cmp.l ($00001008).w,d0 /* did test address #1 get updated? */
bne.s set_8MB /* no, must be an 8MB board */
move.l #$04251987,d0 /* yes, repeat with test value #2 to be sure */
move.l d0,($0000000C).w /* did test address #2 get updated? */
cmp.l ($0000100C).w,d0 /* yes, use the 2MB memcntlr value */
beq.s set_2MB
set_8MB:
move.w #$000A,d6 /* set 8MB memcntlr value */
set_2MB:
move.b d6,(memconf).w /* update memcntlr */
#endif
Re: Suska board
Posted: 20 May 2024 12:29
by Cyprian
There is mem check code in TOS 1.x:
https://github.com/th-otto/tos1x/blob/4 ... tup.S#L344
It looks like it's being made to death... I mean the bus error.
Therefore probably there is no need for any TOS 1.x modifications, and all that is required is to generate the bus error above ST-RAM
Re: Suska board
Posted: 20 May 2024 12:41
by exxos
Cyprian wrote: 20 May 2024 12:29
There is mem check code in TOS 1.x:
https://github.com/th-otto/tos1x/blob/4 ... tup.S#L344
It looks like it's being made to death... I mean the bus error.
Therefore probably there is no need for any TOS 1.x modifications, and all that is required is to generate the bus error above ST-RAM
Good find thanks. I always understood it went to bus error, but couldn't be sure over 4MB.