exxos's Atari, Amiga & retro forum

This is looking pretty amazing. Have you used Altera long? What do you think of the tooling?

Smonson wrote: 20 Jun 2020 06:41 Test render of the next board. It's considerably smaller.
vidout7.png

That looks super sexy! :thumbup:

Aeberbach wrote: 21 Jun 2020 08:44 This is looking pretty amazing. Have you used Altera long? What do you think of the tooling?

Thanks! Since late 2018 when I thought "you know what might be fun? FPGAs!". The IDE, Quartus, is a hefty beast, but at least it runs in Linux. I really just type up verilog documents and compile them without making use of the thousands of other features that appear to be packed into the software. It's all way over my head (I think it's one of those things you really need to have studied at university to get the best use out of).

exxos wrote: 21 Jun 2020 12:21 That looks super sexy! :thumbup:

Thanks Exxos! Hopefully it's the last prototype.

So I decided to try doing something similar, using an Arty A7 with an Amiga. It’s easy to make a VGA output at various resolutions with the dev board.

Sampling the video signal from the Amiga is not as easy but with only a few rates/timings to check not terrible.

But memory access... DDR3 AXI4 is complex! What memory are you using?

Aeberbach wrote: 27 Jun 2020 00:11 But memory access... DDR3 AXI4 is complex! What memory are you using?

I'm using 10nS SRAM. The trouble with DRAM is that it's only fast on average.

Thanks, confirms what I was thinking this the Arty board is great for learning but overkill for VGA. I priced a big SRAM this morning at about $4 :)

The reason I've used 2 ram chips - even though 1 would have been more than enough to hold the amount of data - is because at the pixel clock they're working at the full 32MHz. So I have one dedicated to reading and one dedicated to writing, and then switch RAMs at the end of each scanline. Otherwise I'd have to squeeze in one write and two reads into every 16MHz cycle which is really not easy (I also only have the 32MHz clock to time it off).

I wish there were smaller chips available, but these ones I'm using are 128KB each and I'm only using 2KB out of that. I've used 71V016SA and IS64WV6416EEBLL so far (about $1.70 USD each).

I think I have to reconsider my goals. I wanted to do 8:8:8 RGB for an A1200, deinterlacing with a full buffer up to resolutions around 1024x1024. SRAM for that buffer is prohibitively expensive. A FPGA with sufficient BRAM for even a single line buffer costs even more. DRAM is cheap but is going to be a lot of work and not a viable first project. I think I will try on the A600 and just get it displaying on a VGA monitor to begin with. (If my A600 ever arrives, it’s on the way from France since early May :( )

Why do you need to buffer the entire screen?