@Icky Found a, literally, "small issue" on the IDE header..
ide.jpeg
It seems that is only a issue if using a ribbon cable, the CF connectors don't appear to have any troubles. So this morning I have been tweaking the layout basically moving the IDE connector to the right so it misses the socket better. I don't think is worth re-spinning the board just because of that, otherwise it will push the whole project back some more weeks. I've also shopping around to get the best value on the parts as well.
Speaking of which, I have been trying to get the design to fit into a 1504 for the past couple of weeks as well.
While the majority of IO pins are used.. I was not really using much resources in the PLD.. But it refused to compile into a 1504. Appears to have been the problem was it was compiling the majority of the code into block C: which did not fit.. Whereas the other blocks had relatively little logic used in them. To cut a long story short, I just ended up moving about some IO pins so those inputs would go to a different block, so whereas block A: was 25%, its now 37%... I believe block C: was probably going over product term usage causing the compiler to fail.
Code: Select all
Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanIN Cascades
A: LC1 - LC16 6/16(37%) 5/16(31%) 0/16(0%) 16/80(20%) (26) 1
B: LC17 - LC32 3/16(18%) 14/16(87%) 0/16(0%) 10/80(12%) (27) 0
C: LC33 - LC48 4/16(25%) 16/16(100%) 0/16(0%) 9/80(11%) (28) 0
D: LC49 - LC64 4/16(25%) 8/16(50%) 0/16(0%) 7/80(8%) (26) 0
Total dedicated input used: 1/4 (25%)
Total I/O pins used 43/64 (67%)
Total Logic cells used 18/64 (28%)
Total Flip-Flop used 2/64 (3%)
Total Foldback logic used 0/64 (0%)
Total Nodes+FB/MCells 17/64 (26%)
Total cascade used 1
Total input pins 32
Total output pins 12
Total Pts 42
I did try various compiler options to optimise the logic, but I think there is a bug in the compiler as I believe it totally ignores the "FIELD" variables which are used to decode the address bus.. The "fuse map" ends up being like 75% smaller than when it properly compiles, so I think for some reason the compiler totally ignores logic blocks with the field variables used :roll: So of course I was having a lot of fun with all that.
So the current boards revision R1C will need a small bodge wire on the bottom.. I will post the details about that another time, as currently I did the mod on the original boards to test it out which was not so simple. So rather than a £7 PLD, we can use a £3 one. It may not sound much, but because If I end up buying like 100 of the things, its going to save a outlay of £400 right there.
Icky also found when I fixed the JTAG port issue on the original , I still managed to route it wrong. So the JTAG port basically doesn't work on the R1C boards. Though I will supply a programed and tested PLD with the kits anyway as not many even have a Atmel programmer.
I'm trying to put towards having maybe half built up and half sold as kits. Technically it needs a 68K socket, but if being used on the H4, it doesn't need it. So I am not going to include the socket in the kit, as they are not cheap or easy to obtain any more anyway.
I will need to build one up and test it all works correctly before putting kits in my store yet also. But if all goes well (does it ever?) I hope they will start appearing over the next few weeks.