exxos's Atari, Amiga & retro forum

Badwolf wrote: 11 Aug 2026 14:16 Is this what you intend to run on the new BLUE device (did I remember the name properly)?

It would be interesting to see if the core actually runs on real hardware. But that's another project.. The work did show up some minor discrepancies between the Atari core and Ijors core (the one we are using currently) . Information has been passed over for checking / verification.

exxos wrote: 10 Aug 2026 13:45 The halftone RAM was its own adventure, as the RAM array is a custom layout block that simply is not in the schematic netlist at all, so that had to be modelled from the surrounding decode logic, with each design choice tested rather than assumed.

Hmm, Are you sure? Exactly which Blitter schematics file you were looking? Unless we are talking about different things, the RAM block is definitely there.

Verification is the part I am actually pleased with.
...
The final stage was converting the whole design into a properly synchronous version suitable for an FPGA,

That's an awesome, and not trivial at all, work. Congratulations!

ijor wrote: 13 Aug 2026 02:52 Hmm, Are you sure? Exactly which Blitter schematics file you were looking? Unless we are talking about different things, the RAM block is definitely there.

I've not checked but it might have been the net list. Failing that I was struggling to upload images at the time. So could have been a stale note.

Excellent progress!!! It would be cool to have a plug in replacement for the Blitter as they're hard to find now and expensive!

Great work! :cheers:

So despite all the recent talk of 'AI troubles' in other topics , it does seem to have helped in this case. :)