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:thumbup:Steve wrote: 12 May 2025 20:58 Sorry @exxos it's taken me so long but finally tonight I managed to swap out the Xilinx. Gonna check it for shorts tomorrow and potentially program it.
You need to use YAARTTT as you should be able to find out if there is a bad bit or not.coonsgm wrote: 12 May 2025 22:56 I'm pulling my hair out here reflowing solder points checking for any pin issues. Everything seems good...checked for shorts, checked for non-connected pins going around the PLD about 3 times pin by pin.
Code: Select all
loke ($2000000),12345678
print leek($2000000)Code: Select all
address <= shadow_enable ? shadow_row : { A[23:11] };Code: Select all
wire [12:0] shadow_address = {5'b00111, A[18:11]}; // Maps to 0x4F00000-0x4F7FFFFCode: Select all
assign TOSCE = ( A[29:20] != 10'hE & A[29:20] != 10'h3FE & A[29:3] != 27'h0 ) | ~RW30 | (AS30 & AS) ;
wire ram_disable = 1'b0; // 1 = disable TTRAM
wire ram_area = ((A[29:28] != 2'b00) | (A[27:24] == 4'b0000)) & (TOSCE | ~copy_done | AS30);
assign ram_decode = ram_disable ? 1'b1 : ram_area;Code: Select all
// Address translation: Redirect TOS206 addresses to 0x4F00000-0x4F7FFFF
wire shadow_enable = copy_done & ~AS30 & ~TOSCE; // Enable for TOS206 addresses
wire [29:0] A_INT = shadow_enable ? {7'b0011110, A_IN[22:0]} : A_IN; // Translate to 0x4F00000Copying that address range would require a megaload of counters ... It's best to let the CPU do it. But the copying works fine anyway.. it's when it switches from ROM to TTram it locks up.