exxos's Atari, Amiga & retro forum

So, I think tonight I'm going to get my 16 channel logic analyser and MacBook Pro with the software down from the loft, put lots of paperclips into the PDS slot and record what's actually on the bus. It may show where the problem lies if there's a flat lining data line or the final address (should be the first word of code) shows an obvious bit error.

Seeing as there's a bus error, it's unlikely to be a low address/data bit as that's unlikely to move the address out of the ROM and cause a bus error. The HI ROM is closest to the battery too, so that would have been more affected by the leakage.

Of course, I can't test the address lines to the ROMs from the PDS slot as they come from the VLSI custom chip. Hmmm.

I may have to solder wires to the ROM pins.

It's a pain that they're 16 bit wide ROMs.

stephen_usher wrote: 13 Mar 2024 09:56 Of course, I can't test the address lines to the ROMs from the PDS slot as they come from the VLSI custom chip. Hmmm.

I may have to solder wires to the ROM pins.

It's a pain that they're 16 bit wide ROMs.

This is why I like 8 bit machines so much, just that little bit easier to troubleshoot.

Indeed.

However, it looks like I only really need to concentrate upon the top nibble of the address as the ROM location is 0x40000000-0x4fffffff so that wouldn't generate a bus error if accessed. So, I need to see if the processor is getting a start execution address in that range. If not then either the data from the ROMs is not getting to the CPU correctly or the ROMs aren't seeing the correct address due to connection issues.

stephen_usher wrote: 13 Mar 2024 10:21 Indeed.

However, it looks like I only really need to concentrate upon the top nibble of the address as the ROM location is 0x40000000-0x4fffffff so that wouldn't generate a bus error if accessed. So, I need to see if the processor is getting a start execution address in that range. If not then either the data from the ROMs is not getting to the CPU correctly or the ROMs aren't seeing the correct address due to connection issues.

Can you easily see what address is being requested versus what is at the ROMs?

rubber_jonnie wrote: 13 Mar 2024 11:53 Can you easily see what address is being requested versus what is at the ROMs?

Not without adding wires to the ROM address pins and connecting the logic analyser to those as the ROM address lines are generated by the glue chip and not the main address bus.

stephen_usher wrote: 13 Mar 2024 12:13

rubber_jonnie wrote: 13 Mar 2024 11:53 Can you easily see what address is being requested versus what is at the ROMs?

Not without adding wires to the ROM address pins and connecting the logic analyser to those as the ROM address lines are generated by the glue chip and not the main address bus.

Not a fun thing to do...

OK, here's what the bus is doing...


This makes very little sense. From what I remember the first three words read by the 68030 should be: vector table address, interrupt table address, stack and program pointer before it starts executing code, or similar.

The ROM should sit at 0x40000000 to 0x4fffffff so any valid addresses for the program counter should be in this range, which is why I chose to look at D28-D31, the top nibble.

I think that A1 not toggling is a little suspicious... Hmm.

Yes, nothing on A1 is suspicious, but I see also that you’re sampling at 50 MHz which might be close to the limit for a 25Mhz signal. You might want to sample at 100Mhz to make sure you don’t miss quick transitions.