exxos's Atari, Amiga & retro forum

That 48 char mod makes it look so much better.

PhilC wrote: 11 Apr 2024 15:21 That 48 char mod makes it look so much better.

Yeah, it is soooo much better.

The only issue is that the left hand margin is controlled by a value set in ROM, and if I swap to a different display, the margin is off the left hand side. I can do different ROMS that work with different displays, but it's a bit annoying.

OK, back to cassette interface again.

This is the schematic for the cassette out:


What I know so far is as follows:

U64 pins 2,4 and 16 are receiving the data that is to be saved to cassette as expected.
U64 pins 1 & 6 are getting a clock signal of 4.8Khz
U64 pin 15 is outputting a signal of 2.4Khz. This is also seen at pins 9&12.
U64 pin 11 is outputting a signal of 1.2Khz, however it is unaffected by the signals coming into pins 2,4 & 6.
U69 pin 1 & pin 4 have a signal that is present during a save which looks similar to the save data, and stops when the save stops.

R50 and C12 are correct as is R86, R56, R55, R54 and C13.

Looking at the datasheets for U64 & U65, the only thing I can say is that CLR is held high all the time across both IC's (R86 does this), and they are active low. Should they ever go low? Not sure, bit of a head scratcher.

Yout have got a 74LS76 and not a 74LS76A haven't you? The truth tables are quite different and with an A variant the K and J values are ignored by the second stage.

stephen_usher wrote: 16 Apr 2024 12:19 Yout have got a 74LS76 and not a 74LS76A haven't you? The truth tables are quite different and with an A variant the K and J values are ignored by the second stage.

Screenshot_20240416_121850.jpeg

P.S. Putting a logic analyser onto U64 pins 6, 7, 8, 9 and 11 would be useful as the relative timing of these signals is important, which you can obtain in no other way.

stephen_usher wrote: 16 Apr 2024 12:19 Yout have got a 74LS76 and not a 74LS76A haven't you? The truth tables are quite different and with an A variant the K and J values are ignored by the second stage.

Screenshot_20240416_121850.jpeg

Hmm, it was actually an 74LSAN, I have swapped for a 7476 and no different. Will see if I have another non 'A' LS in my drawers.

Ho hum.

stephen_usher wrote: 16 Apr 2024 12:26

stephen_usher wrote: 16 Apr 2024 12:19 Yout have got a 74LS76 and not a 74LS76A haven't you? The truth tables are quite different and with an A variant the K and J values are ignored by the second stage.

Screenshot_20240416_121850.jpeg

P.S. Putting a logic analyser onto U64 pins 6, 7, 8, 9 and 11 would be useful as the relative timing of these signals is important, which you can obtain in no other way.

Might have to do that later. Back to work now.

I've been getting a lot of great help from the folks at OSIweb.org, you can see the main post from over there here: My Klyball 600D build

Based on what I'd been told over there, I went back and double checked and noticed something I'd missed earlier. Pins 2,4 & 16 of U64 were not starting out low, but actually at about 4v. Everything else was as it should be at U64.

So I checked the output of the 6850 on pin 6, that was high as was the input to U18, pin 13. However the output from U18, pin 12, which should have been low having gone through the inverter, was actually 4v and when I ran POKE 61440,241 (This sets pin 6 of the 6850 to low), it went up to 5v.

This was reflected at pins 2,4 & 16 of U64.

I swapped out U18 for a replacement, and U18 pin 12 now correctly reflected what was happening at the 6850, being low at idle, as were 2,4 &16 at U64.

I tested the 74LS04 that came from U18 and it was dead. So the low on the bad U18 was 4v and the high was 5v, meaning there was never a proper transition between low and high, so although the data pulses were seen at 2,4 & 16 of U64, they were always high.

Now if I hook up to pin 9 or 7 of J2 and feed them into my speakers, I get an actual output when I save :)

Next I need to test the cassette input and see if that works now that I can save.

Phew! :-)

stephen_usher wrote: 18 Apr 2024 12:04 Phew! :-)

It's a good first step, but I'm not out of the woods just yet. I also need to get the cassette input working, and it isn't...


So this is the first stage of the cassette in port, and testing is quite simple as it goes.

First you jumper pin 9 (AUX) and pin 10 (MON) of J2 together. This connects the AUX out to the cassette in.

Next comes a small testing routine:

10 PRINT "U";
20 GOTO 10
SAVE then enter
RUN then enter

This just prints U on-screen, but due to the weird way SAVE works, it can be used to generate output from the cassette port.

SAVE is weird, because what you do is type the SAVE command into BASIC and then hit enter. The machine changes into SAVE mode. By then typing LIST and hitting enter, it lists your program and sends the data via the 6850 to the cassette port. You can't save a program by name, such as 'SAVE "PRG_NAME", it doesn't work that way.

Very odd, but it helps us here because we are printing "U" to screen and that is sent via the 6850 to the cassette port as though we were listing a program to save it, so what's coming out of AUX is going straight into pin 10, the monitor jack.

However, looking at U66, I see input at pin 2 which looks great. Pins 3 & 4 are grounded as per the schematic, pin 7 has 5v, and the capacitor across pins 1 & 8 measures correctly at 68pF.

All fine thus far, but no output at pin 6. So I thought I should check C6 and found that it's 150nF not 150pF. I'm pretty sure this caught me out before, so I'm going to swap it out and see if that helps.

If there's no change, then I guess the CA3130 is dead, another victim of me overvolting the board most likely. Dumb of me I know, but what can you do other than replace what you killed. Let's see if it's the cap first.