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Re: BLITTER RE-CREATION THOUGHTS
Posted: 04 Nov 2021 13:09
by mmx01
As starting point I took Suske BLT101643 (WF101643IP_TOP), compiled no problem with Quartus 18.0. Noticed there are two versions, one which seems to be stand-alone IC and the other one probably integrated with other ICs in the same FPGA chip judging by additional signals and pins.
Re: BLITTER RE-CREATION THOUGHTS
Posted: 04 Nov 2021 14:05
by exxos
Suska is what we are using to start with ( I have permission from Wolfgang to use his core)
Basically goes back to this post..
https://www.exxosforum.co.uk/forum/viewt ... 180#p24704
Re: BLITTER RE-CREATION THOUGHTS
Posted: 05 Nov 2021 09:41
by mmx01
I see, so PLL is clocked by either 8 or 16MHz from ST as external clock without an oscillator. Interesting as there's one on Suska stand-alone IC board. GTL is open drain so no extra diodes or logic required for DTACK etc, 200k for pull-up of D/Gref.
If there would be ready product to buy I would spare my time but seems it needs to be hard way again, and that PLCC-ish socket again ;)
Re: BLITTER RE-CREATION THOUGHTS
Posted: 05 Nov 2021 11:07
by exxos
Indeed. There are chip shortages and lack of time for us to work on it right now. I've said it all before. Of course when we have some spare boards and people are willing to spend the time on it...
Re: BLITTER RE-CREATION THOUGHTS
Posted: 08 Nov 2021 21:39
by mmx01
Kind of short on real estate due Cyclone IV being a large chip with tons of needed voltages plus external flash but this is what I have. Creation of blitter library with Atari PLCC socket... lovely part due HD copies of schematics and no doubts on pinout ;)
This is still prior optimization but was unable to fit it on a 2 layer board due voltage shifters doubling signals and very close to edge connector on Mega. Auto router made havoc so 100% manual routing with kind-of similar length for signals but at 8Mhz don't consider this a big thing.
Layer 3 is a ground plane to help a little bit with chips sitting above each other and regulators noise. Kudos to layout engineers out there. Header connector will get removed after this moves from early dev to persistent dev state. Looks like it won't fit my ST with JTAG connector while in the case due joy ports plastic cover. Perhaps I'll change it to "saw off"option.
brd.png
rev1.jpg
blitter.png
Re: BLITTER RE-CREATION THOUGHTS
Posted: 09 Dec 2021 20:42
by mmx01
And here we are. 4 layer boards turned out okay from Aisler but only 2 out of 3 passed the testing at the factory... wondering will I ever get my 3rd board :roll:
pcb.jpg
Assembled and fitted this to my Atari Mega ST 1. Almost stock, 8Mhz , 4M upgrade and TOS 2.06 hack.
assem.jpg
Thankfully no board hacks were needed after revision 5 (all virtually checked so no cost impact).
The good - it is working. Short blitter cartridge test fails but long one works. The computer is stable, blitter is selectable in GEM and otherwise cooperates with testing tools and the computer. Strange issue with I/O access was definitely caused by the original blitter failing as no such issues appear with fpga one. It is based on the core from SUSKA to which I only added LED routine for now to see if entire thing is not brain dead ;)
The bad - results are so-so. Still considerable gain versus no blitter but if I read comparison right (comparing to MSTEB8) blitter is at 97%. I know test data of MSTE8 is STE not ST but I don't consider this material for blitter test. Overall with blitter disabled graphic performance is at 70% of MSTEB8, enabled 106%
cmp.jpg
Comparing to ST with no blitter
blten.jpg
Interestingly it accelerates other graphic tests too > 100% but with blitter disabled they are in the 70-80% range.
Re: BLITTER RE-CREATION THOUGHTS
Posted: 09 Dec 2021 20:54
by exxos
:bravo:
You need to run in Medium res as the tests you are comparing are not really valid.
These are the results you should be seeing
https://www.exxosforum.co.uk/forum/viewt ... f=42&t=566
Aisler - don't use them. Screwed me over!
Re: BLITTER RE-CREATION THOUGHTS
Posted: 09 Dec 2021 21:38
by Icky
:bravo:
@mmx01
You should run a GEMBench test on your ST in med res with an original blitter in and save the test file. Then run with the recreation and see the comparable speed. It will probably be 97-98% and this is where we got to. It is now down to the timing etc.
Can you run these programs from
@Cyprian that map out the timing and cycles etc. and post your images so we can compare. See if you have got to the same point we are at.
https://www.exxosforum.co.uk/forum/viewt ... 260#p28439
https://www.exxosforum.co.uk/forum/viewt ... 300#p51391
Re: BLITTER RE-CREATION THOUGHTS
Posted: 10 Dec 2021 10:17
by mmx01
Thanks for the tip re. resolution. I don't have working original blitter to make such comparison so can only compare to other sets of test data. Will rerun with med res though.
Re. where I am, no surprise at the same starting point. Timing is off but that's the next step. First was to get it going at all and see if that was original blitter IC that was wrong or something else on the board.
20211210_101655.jpg
Re: BLITTER RE-CREATION THOUGHTS
Posted: 10 Dec 2021 14:08
by Badwolf
Excellent progress on a noble project, @mmx01 !
BW