exxos's Atari, Amiga & retro forum

Chatting elsewhere it seems that I only have to worry about the top two address lines.

So, I either need (/A19 AND A18) OR (A19 AND /A18) (i.e. either 01 or 10 but not 11).

This morning I had an Idea.. Why don't I plug a logic analyser into the external expansion port and see how the bus control lines operate. I should be able to just push the wires onto the pins!...

Then I realised that I had glued the expernal port door to the main case to support the parts which were missing. D-oh! Of well, it was a nice idea. :-)

stephen_usher wrote: 26 Aug 2021 14:31 This morning I had an Idea.. Why don't I plug a logic analyser into the external expansion port and see how the bus control lines operate. I should be able to just push the wires onto the pins!...

Then I realised that I had glued the expernal port door to the main case to support the parts which were missing. D-oh! Of well, it was a nice idea. :-)

Can you not pick the connections up internally? Or is it too much of a faff?

Yeah, I can use the internal expansion port, but that's a female DIN 41612 connector. Once I get the connectors which will eventually be on the expansion board I can connect the wires to the pins on there. It's not a major problem but I can't do it today. :)

stephen_usher wrote: 26 Aug 2021 15:52 Yeah, I can use the internal expansion port, but that's a female DIN 41612 connector. Once I get the connectors which will eventually be on the expansion board I can connect the wires to the pins on there. It's not a major problem but I can't do it today. :)

Fair enough

Last night I managed to lash up a connection for the internal expansion port (hopefully not damaging the port) and connected the 16 channel logic analyser.

The data makes it look like using the address lines may be more complicated than I thought.


A quick overview of the signals:

• /MRDC and /MWTC are memory read and write
• /IORC and /IOWC are the IO equivalents
• ALE (Address Latch Enable) is the line from the CPU supposedly saying that there's a valid address on the bus.
• DT/R is said to be "data transmit/receive" which is supposed to be the direction of data flow from a peripheral(??)
• /RES the system reset line
• DEN "data enable", which is essentially a bus grant line

The trouble is, as you can see, the timing between ALE and the other bus control signals and the address lines is, let's say, a bit inconsistent!

It seems as if the best predictor of a valid address, at least for memory, is the DEN and /MRDC or /MWTC signals.

Can anyone else make head or tail of this?

Right. I think that I've probably worked this out.

I can use a set of three 74LS373 octal D-type latches and put them on the address lines. Then use the ALE signal to latch them onto the internal bus.

I should also probably latch the other addressing signals as well, such as /BHE and /BLE for consistency.

In that way whenever there's read or a write cycle then I can use a "valid" address. The "address valid" is then when ALE is low, as the address lines are in transition during any time that ALE is high and the latches are following the system address bus.

Well, I think that's how it should work.

Well, the RAM board design is starting to come together now. I'm going to be adding a header for a daughter board so that I can later design an emulation of the original "winchester disk" interface (which used an WD1010A controller). This is why I'm allowing the control of the address latches so that the daughter board can make use of the RAM whilst the CPU is doing other things.

Too complex for one GAL, so having to separate the system memory decode into one GAL and bus control into another, and then buffer the memory chip control so that the expansion card can do interl reads and writes to the SRAM chip, when the CPU isn't accessing it.

Does anyone know where I can find a KiCAD footprint library for an 8 pin DIN socket, PCB mounted, right-angle?

i.e.