Re: Shifter LOAD behaviour
Posted: 28 May 2025 02:09
I'm not sure if it would be of use, but the verilog shifter model that I based on ijor's schematics was split out into its own repo here: https://github.com/smonson78/st-shifter-verilog
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Thanks Smonson! It probably doesn't have a direct application but it's certainly useful!
I would probably recommend that you run the simulations and then look at the waveforms in GTKWave. That allows you to see not only what's going on with the input & output pins, but also shows what's in the internal shifter registers. It's also super easy to edit the test file to create any extra scenarios that you had in mind. No need to infer!Badwolf wrote: 28 May 2025 10:02 Since I'm trying to read the output of that and back-infer what it's doing to have a blow-by-blow breakdown of what it's doing is most helpful indeed.
Thanks, yes, I'll do that.Smonson wrote: 28 May 2025 11:29 I would probably recommend that you run the simulations and then look at the waveforms in GTKWave.
I only meant what my CPLD is doing. It's going: "aha, this is the seventeenth LOAD instruction since VBLANK, so this must be screen address offset 32".No need to infer!
+1. A very wise advice.Smonson wrote: 28 May 2025 11:29 I would probably recommend that you run the simulations and then look at the waveforms in GTKWave.