exxos's Atari, Amiga & retro forum

I think it may be possible, despite delays.
The YM goes tri-state whenever there is invalid address on the high bits (i.e. different from %0000xxxx)

Scenario:

The 68k sets bdir & bc1 & address %0001xxxx
YM0 ignores this, as address is not 0000
YM1, because of delay on the D4 line, also sees 0001, so ignores.
then D4 goes low (gets inverted by our additional circuitry) and YM1 sees 0000 and that's a valid address/bdir/bc1 combination, and so it latches the register address and awaits the next bus change for the data.
now 68k sets bc1 low and puts data on the bus.
this is the interesting part:
bc1 low is immediately available on YM1, but D4 may have a short delay. Will the YM now store the data immediately into its running register or wait until the bus cycle is finished (and D4 has stabilized)

I'm not a geniouns in reding data sheets, the timing is specified.
But it's a slow chip for s slow 8 bit system. Is it slow enough to not even see the latency on D4?

When does the YM decide that its data is good? Maybe only after Tdw is over? That would give plenty of time, and so we are fine.
times are: ______________________________________________________ | min | typical | max | units

I had some fun, if you need to learn a new software. Quite surprised what today's online tools are able to do.

So I proudly present the circuit nobody needs or wants: 16 YM2149 adaptor for AtariST. :lol:
Here is the website, it can even simulate, on condition to use elements which are made for that (not the case here).
https://easyeda.com/Gunstick/16ym-circuit

PS: I'm even not sure I connected it all correctly.

Gunstick wrote: 04 Nov 2019 14:57 The 68k sets bdir & bc1 & address %0001xxxx
YM0 ignores this, as address is not 0000
YM1, because of delay on the D4 line, also sees 0001, so ignores.
then D4 goes low (gets inverted by our additional circuitry) and YM1 sees 0000 and that's a valid address/bdir/bc1 combination, and so it latches the register address and awaits the next bus change for the data.

Neither YM will ignore address sets (both BDIR and BC1 set to 1) regardless of the values seen on the data bus, they should simply latch whatever data they are seeing on the data bus (plus the two additional address pins).

It's not until a register read (BDIR = 0, BC1=1) or register write (BDIR=1, BC1=0) that the YM inspects the latched address, and will ignore the request iff the 10 bit address does not match %(01)0000xxxx. (If they'd ignore the address latch, they wouldn't know that they should ignore the subsequent read/write.)

Additionally I'm sure that the chips will only latch the address once (either on the rising or falling edge of BDIR/BC1 changing, or even tied to the clock input.)


But it's all related to timing, and there is a chance that all the bits do get to settle before the relatively slow YM acts on them... and that they stay stable long enough too.

Also in your scenario you assume that YM1 initially sees 1 at bit position 4, but since the BDIR/BC1 pair most likely went from 0,0 (idle) to 1,1, all buffers and switches connected to the modified DA4 pin will have been tri-stated and the value just prior to the inverter being activated is unpredictable. I do expect the tri-state inverter to be much faster than the YM, so it will never experience that, however, so it should "just work(tm)"

I will get myself a couple YMs and components and cobble together something to check if it works.

Gunstick wrote: 06 Nov 2019 08:53 I will get myself a couple YMs and components and cobble together something to check if it works.

You are a brave man. Hope it works out. In case you don't want to fiddle with that analog switch stuff, you might like my latest sketch. It has extra wires out for DA4/5 for the chips that don't need the bit reversed as well as the flipped one.
By the way the 74x2gNNNs could probably just be replaced by a normal DIP 74LSNNN (and the 74AUC* ones in there should at least be LVC instead)

This is turning into a nice little project. Maybe this could be a good upgrade for exxos's next Atari

keli wrote: 06 Nov 2019 19:33
You are a brave man. Hope it works out. In case you don't want to fiddle with that analog switch stuff, you might like my latest sketch. It has extra wires out for DA4/5 for the chips that don't need the bit reversed as well as the flipped one.

I don't understand exactly this circuit. Is DA4_0 the normal signal and DA4_1 the flipped one?

Does this require the original YM's pins for DA4 (and DA5) to be cut from the mainboard?

Gunstick wrote: 11 Nov 2019 23:13

keli wrote: 06 Nov 2019 19:33
You are a brave man. Hope it works out. In case you don't want to fiddle with that analog switch stuff, you might like my latest sketch. It has extra wires out for DA4/5 for the chips that don't need the bit reversed as well as the flipped one.

I don't understand exactly this circuit. Is DA4_0 the normal signal and DA4_1 the flipped one?

Does this require the original YM's pins for DA4 (and DA5) to be cut from the mainboard?

Correct. Although I would have created a board that plugs into the original socket and the original YM would be moved to one of the 4 (or 2) sockets on the board.

I think the previous design does not need cutting DA4 & DA5 so the whole board could be piggybacked on the existing YM, sparing you painful unsoldering and also no pin cutting. But maybe I am wrong?

I'm currently looking for simulation and pcb software for linux. Found kicad with ngspice, but did not yet install it, as it looks quite complex.

Just found this thread because I'm tinkering with the YM2149 on other comuters (and fake AY chips).

Another solution that would be easier to implement is actually to use a YM2203 which is YM2149 compatible. The pinout is different but basically with a small adapter it could act like a YM2149 replacement. Then by adding a small DAC you can add 3 FM channels.
The extra registers are addressed the same way than on YM2149.

Then to go further you can try replacing the YM2149 by a YM2608, you get then 3 PSG + 6 FM channels + ADPCM replay. Again a DAC is needed to get the FM part.

Note that there's surely things to look out when putting a YM2203 or a YM2608 in an ST but my guess is that the hardware adapter part should be minimal, except if you use the ADPCM feature of the 2608 (which needs access to an external memory it seems).