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Re: TF CD32 Riser Revision 2 Design Complete

Posted: 12 Oct 2020 23:37
by terriblefire
arkadiusz.makarenko wrote: 12 Oct 2020 23:13 That is what I did try, already.
I need to measure exti latency....

I even can't read meaningful data from the bus. :(
Time for a break and regroup I think. :D ... it was worth a try. (Need to get a little bit better with verilog)
EXTI latency is not the issue. It could sit there for a month... no issues. You want it to be short for performance but You read the mouse and joystick once every 1/50th of a second and you read the RTC once at boot time. So speed isnt critical.

The issue is that when you ACK the ARM is still putting data on the bus. So the next instruction fetch crashes.

I suspect the bus isnt getting tristated again.

You could try put data on the bus... when you ack latch it into the cpld... then read it from the cpld on some other random address.

Re: TF CD32 Riser Revision 2 Design Complete

Posted: 13 Oct 2020 09:08
by arkadiusz.makarenko
terriblefire wrote: 12 Oct 2020 23:37
arkadiusz.makarenko wrote: 12 Oct 2020 23:13 That is what I did try, already.
I need to measure exti latency....

I even can't read meaningful data from the bus. :(
Time for a break and regroup I think. :D ... it was worth a try. (Need to get a little bit better with verilog)
EXTI latency is not the issue. It could sit there for a month... no issues. You want it to be short for performance but You read the mouse and joystick once every 1/50th of a second and you read the RTC once at boot time. So speed isnt critical.

The issue is that when you ACK the ARM is still putting data on the bus. So the next instruction fetch crashes.

I suspect the bus isnt getting tristated again.

You could try put data on the bus... when you ack latch it into the cpld... then read it from the cpld on some other random address.
Now I got triggered. :D

I must do something really stupid there...

Re: TF CD32 Riser Revision 2 Design Complete

Posted: 13 Oct 2020 10:39
by arkadiusz.makarenko
BUAHAHAHA!!!!! It's ALIVE :D

20201013_103803.jpg

Edit: I was not handling DSACK correctly. This one hold 0/1 high till ARM tell it to change DTACK0 to low.

And on ARM side I do reprogram gpio back to open drain before I send ACK to CPLD. It must takes few cycles before it actually happens so cd32 have enough time to latch data.

Re: TF CD32 Riser Revision 2 Design Complete

Posted: 13 Oct 2020 11:07
by terriblefire
Nice work. Now you can do everything you need from ARM. just used different INTSIG for different addresses.

Re: TF CD32 Riser Revision 2 Design Complete

Posted: 13 Oct 2020 14:28
by terriblefire
terriblefire wrote: 13 Oct 2020 11:07 Nice work. Now you can do everything you need from ARM. just used different INTSIG for different addresses.
If you tell me all the pcb changes needed for the RTC and Vcap i'll update the github repo

Re: TF CD32 Riser Revision 2 Design Complete

Posted: 13 Oct 2020 15:28
by arkadiusz.makarenko
terriblefire wrote: 13 Oct 2020 14:28
terriblefire wrote: 13 Oct 2020 11:07 Nice work. Now you can do everything you need from ARM. just used different INTSIG for different addresses.
If you tell me all the pcb changes needed for the RTC and Vcap i'll update the github repo
I will, but need to get my head round all RTC options. Just touched the subject few months ago. Need to refresh my memory on it.

Re: TF CD32 Riser Revision 2 Design Complete

Posted: 13 Oct 2020 15:38
by terriblefire
arkadiusz.makarenko wrote: 13 Oct 2020 15:28 I will, but need to get my head round all RTC options. Just touched the subject few months ago. Need to refresh my memory on it.
No worries. I think you mentioned you needed another oscillator?

I'll sort the video out and let you get back to me on the oscillator.

Re: TF CD32 Riser Revision 2 Design Complete

Posted: 13 Oct 2020 15:43
by terriblefire
I'm considering this part for buffering the video output..

https://uk.rs-online.com/web/p/video-buffers/4972511/

and

https://uk.rs-online.com/web/p/video-buffers/1627539/

May end up going with a part that JLCPCB has supply of rather that the "best" chip.

e.g.

https://datasheet.lcsc.com/szlcsc/3PEAK ... 155447.pdf

Re: TF CD32 Riser Revision 2 Design Complete

Posted: 13 Oct 2020 17:15
by terriblefire
I have pushed the changes for the Vcap to github. let me know if you want the crystal changed etc.

Re: TF CD32 Riser Revision 2 Design Complete

Posted: 13 Oct 2020 20:30
by terriblefire
We need to figure out what you meant here..

https://www.exxosforum.co.uk/forum/viewt ... d32#p37462

LSE oscillator was missing i think?