exxos's Atari, Amiga & retro forum

Badwolf wrote: 07 Apr 2021 10:48 Yes! That's *got* to be the tipping point.

It seems TTRAM access for some reason happens too fast. When it's not working, TTRAM hits 903%, not 847%. So I think STERM is ever so slightly too fast. Inverting the 100mhz clock does the trick. What I may try is clocking STERM via a FF to delay it 10ns to see what happens. I assume worst case the score would drop. But if inverting the clock is enough to fix / break stuff, something is very borderline.

So what's next... 60mhz ... :lol: :hide:

exxos wrote: 07 Apr 2021 13:02

Badwolf wrote: 07 Apr 2021 10:48 Yes! That's *got* to be the tipping point.

It seems TTRAM access for some reason happens too fast. When it's not working, TTRAM hits 903%, not 847%. So I think STERM is ever so slightly too fast. Inverting the 100mhz clock does the trick. What I may try is clocking STERM via a FF to delay it 10ns to see what happens. I assume worst case the score would drop. But if inverting the clock is enough to fix / break stuff, something is very borderline.

So what's next... 60mhz ... :lol: :hide:

Bear in mind the SDRAM is synchronous on the positive edge and the 030 on the negative. Inverted is probably the optimum, therefore as the data should be valid between the falling edge 1.5 cycles after CAS is latched and the falling edge 2.5 cycles after CAS is latched.

But AIUI your SDRAM is running at twice the CPU's frequency, so you're on your own!

BW

PS: my ceramic 030 (purchased just six months ago from your very boutique!) can't get beyond about 55MHz and I can barely keep the SDRAM in sync at 50!

Badwolf wrote: 07 Apr 2021 17:11 But AIUI your SDRAM is running at twice the CPU's frequency, so you're on your own!

PS: my ceramic 030 (purchased just six months ago from your very boutique!) can't get beyond about 55MHz and I can barely keep the SDRAM in sync at 50!

Challenge accepted! ;)

Meanwhile,

Somewhere in the UK @exxos has just pressed the reset button on his 60mhz 030.

For the avoidance of doubt.. the SDRAM controller sends for 2 reads when it runs at x2 cpu speed. It’s done this way because the required delays are in clocks not ns.

111.1MHz clock (55.55Mhz CPU)

117.6MHz clock (58.8Mhz CPU)

exxos wrote: 07 Apr 2021 22:23 117.6MHz clock (58.8Mhz CPU)


IMG_6398.JPG

Nutcase.. :D

122.2MHz clock (61.1Mhz CPU)

SDRAM Was being a bit sulky , so I had to invert the clock again to get it to work, so these results ended up being less other than actual integer division and TTram speed... or maybe if I crank up the speed some more it will work back with the inverted clock... :twisted: :twisted:

terriblefire wrote: 07 Apr 2021 22:25 Nutcase.. :D

You still love me though :lol: :fire: :fire: :fire: