mikro wrote: 03 Jan 2025 18:49
While we are on the topic of chips removal: what about the FPU? Not sure whether it was on Exxos page or your wiki but somewhere it was recommended to remove it due to bus conflicts. Is this still true with the Exxos version? If so, would you mind to explain why it's not a problem for TOS ROM (well, except the one described above ;)) but it is for the FPU?
Sure. I recommend removing the onboard FPU as
I think it gets activated whenever the external 030 hits its own FPU. That isn't to say it would work if the external one isn't there as I've stopped the address strobe reaching it, but I think I worked out the GALs trigger the FPU enable line purely on the DS strobe, which is not isolated.
Now I'm not 100% sure sure that directly implies the onboard FPU does come out of high-z mode at all, but it would not surprise me if it did and it ties in to some FPU related problems people were having.
The reason I say 'I think' and 'it may' is that I've not actually probed the onboard enable line nor have I read the datasheet in enough detail to know what effect active enable and DS lines without a corresponding AS line would have on the FPU's pins.
Unfortunately I only worked out the FPU GAL logic after implementing my board design so there's no firmware fix for this. Safest to pull the onboard FPU to prevent short circuits somewhere.
Now the ROM on the other hand is relied on threefold. Firstly, when the blitter tries to take anything from ROM it only has access to the onboard version (see Atari logo problem, above), secondly there is a 'disable flash' option which will need the OS to come from somewhere [the flash chip itself is entirely optional] and lastly when DFB1 is in disable mode (eg. to allow flashing, or to revert to stock configuration) the flash ROM is remapped to the expansion address range, so a real ROM is needed to step in.
Btw how sensitive would the DFB1X be to 50 MHz DSP? If it worked, that would surely increase backward compatibility with DSP demos, mine included. :)
Gosh, sorry I've no idea.
The DSP is a bit of a funny one and the very last thing I got to work. There's a long post on it somewhere. It turns out the DSP latches on the deassertion of the write cycle rather than at the start of it and that cycle is controlled by the GALs. I have to therefore stall one (or two?) of the lines by half a cycle so that data is still valid on the bus when the GALs shut down the control lines.
If that timing is altered it's possible it could help (chip deasserts faster, data effectively valid longer) or hinder (half a 16MHz clock cycle is a long time for a 50MHz DSP). If I had to guess I'd say it'd
probably be the former, but I wouldn't put much money on it!
I suspect it could be made to work if it didn't, but I'm afraid it'd need someone with a scope and time on their hands!
BW