exxos's Atari, Amiga & retro forum

All I can say is "superb!", and thank you Terriblefire :D

Danoo wrote: 27 May 2020 11:37 All I can say is "superb!", and thank you Terriblefire :D

Well all i've done so far is make a scribble and order it.. the work is yet to come.

terriblefire wrote: 26 May 2020 09:09Should be possible to tweak the design it to any PLCC part for ST's and Amigas.

that's a great news, would be cool to have it in the ST

terriblefire wrote: 26 May 2020 09:09 Design is an ICE40HX4K FPGA + Level Shifters. It solders into a PLCC TH socket like Megachip. I'm sure someone will ask why I didnt put ram on here.. Simple. I'm a purist. I want this chip to replace Agnus and nothing else.

Nice. Slightly confused with the above, is it soldered to the motherboard or have you found a PLCC84 male plug (like MegaChip)?

Do you foresee any startup delay issues with the FPGA reading its flash and not being ready fast enough for the system? Or maybe it can hold reset line?

richx wrote: 27 May 2020 17:13

terriblefire wrote: 26 May 2020 09:09 Design is an ICE40HX4K FPGA + Level Shifters. It solders into a PLCC TH socket like Megachip. I'm sure someone will ask why I didnt put ram on here.. Simple. I'm a purist. I want this chip to replace Agnus and nothing else.

Nice. Slightly confused with the above, is it soldered to the motherboard or have you found a PLCC84 male plug (like MegaChip)?

It just solders into the the TH sockets. You must remove the PLCC socket first.

I've never seen a megachip with a male PLCC connector but i suppose they may exist.

Do you foresee any startup delay issues with the FPGA reading its flash and not being ready fast enough for the system? Or maybe it can hold reset line?

Probably not an issue because Agnus generates the 7Mhz clock. So until its up and running the CPU stays dormant.

terriblefire wrote: 27 May 2020 17:32 Probably not an issue because Agnus generates the 7Mhz clock. So until its up and running the CPU stays dormant.

Agnus has a reset pin anyway, so you can pull reset low with an open drain output for 0.5s after the FPGA has initialised & clocks are up. (i.e. guarantee a graceful power up)

cmorley wrote: 27 May 2020 18:47

terriblefire wrote: 27 May 2020 17:32 Probably not an issue because Agnus generates the 7Mhz clock. So until its up and running the CPU stays dormant.

Agnus has a reset pin anyway, so you can pull reset low with an open drain output for 0.5s after the FPGA has initialised & clocks are up. (i.e. guarantee a graceful power up)

Its tricky to pull things low before you've been programmed but i would need to hold reset low until the PLLs are all locked in the FPGA anyways.

terriblefire wrote: 27 May 2020 19:44 Its tricky to pull things low before you've been programmed but i would need to hold reset low until the PLLs are all locked in the FPGA anyways.

Indeed.

No need to engineer anything to hold reset low before the FPGA is configured. Pull it low as soon as it is configured then release it when the clocks are good. Gracefull boot every time.

Does the A500 keyboard do a reset pulse (via Gary) on power on? If so I'd wager the FPGA is ready before that is over (0.5s pulse on A500)! All I'm saying is to the curious thread readers the FPGA config & reset really isn't a concern. For the curious you get a head start with the configuration against the Amiga because the 1v2 Vcc and VccIO etc will be good before the miggy 5v even hits 5v using LDOs.

Exactly. This is the heart of the machine so everything else has to wait for it to be ready anyways.

Worrying about this sort of thing is what stops projects happening. Just build it and see.

Nice board and project @terriblefire.

Wish I had the time to get back onto the Blitter, MMU and GLUE boards we are working on for the ST.