exxos's Atari, Amiga & retro forum

Out of curiosity - the FPU ICs you have both been using for your experiments - what clocks are they rated for? Are they FN16, FN25, FN33 or FN40s?

dml wrote: 17 Nov 2022 07:46 It looks like nonsense but its actually a close up of this fractal, at some random orientation:
...
Each time it redraws (slowly) it has rotated some amount. That's all really. FPU should be toasty after a while!

Oh wow. Very cool, but now I know what it does, I don't plan on waiting for the movie. :lol:

I will let it run a full screen tomorrow, though :)

BW

dml wrote: 17 Nov 2022 08:16 Out of curiosity - the FPU ICs you have both been using for your experiments - what clocks are they rated for? Are they FN16, FN25, FN33 or FN40s?

They all FN40 but as they from China.. Who knows.

dml wrote: 17 Nov 2022 08:16 Out of curiosity - the FPU ICs you have both been using for your experiments - what clocks are they rated for? Are they FN16, FN25, FN33 or FN40s?

All mine have been branded FN40, but I've only ever owned one that passed your tests at 40MHz (it's normally the trig functions that fail first). Sadly, one evening during development, I inserted that particular hallowed chip into my DFB1r4 booster rotated at a 90 degree angle to that intended.

Things got warm quite quickly.

My current chip can now only go at 30. The third chip I owned (presently residing in the on-board FPU slot under the PSU) couldn't even make the 25MHz of an OSC/2 divider.

BW

@exxos, an opnion from you, if I may:

Could the below condition be (electrically) tolerated for any length of time, do you think? I'm thinking minutes not hours.

Obviously the FPU wouldn't work, getting potentially a very high and irregular clock, but I'm just musing over soft-clock options and whether I should support the below configuration until software can turn off the CPLD clock (the 3V OSC in this diagram).

Ta,

BW

Badwolf wrote: 17 Nov 2022 10:08 Could the below condition be (electrically) tolerated for any length of time, do you think? I'm thinking minutes not hours.

Obviously the FPU wouldn't work, getting potentially a very high and irregular clock, but I'm just musing over soft-clock options and whether I should support the below configuration until software can turn off the CPLD clock (the 3V OSC in this diagram).

Not sure I really follow there sorry.. I talk about using the PLD switch enable signals on the oscillators ? but if you are going to that you might as well just switch the clock lines directly..

exxos wrote: 17 Nov 2022 10:20 Not sure I really follow there sorry.

I'm asking you if you think any damage would be done to the OSC, the FPU or the CPLD if both were driving at the same time in a Y-configuration via a 33R resistor on each leg.

I'm referring to the current board layout and what I can get away with supporting in firmware only change. This is an error condition, but would it be survivable until software can intervene?

BW

Badwolf wrote: 17 Nov 2022 10:24 I'm asking you if you think any damage would be done to the OSC, the FPU or the CPLD if both were driving at the same time in a Y-configuration via a 33R resistor on each leg.

That is what happened on the Falcon... We don't want to do that :)

Badwolf wrote: 17 Nov 2022 10:24 I'm referring to the current board layout and what I can get away with supporting in firmware only change. This is an error condition, but would it be survivable until software can intervene?

I would assume it would survive for brief periods.. But it is not a failure mode I really looked into. If you are of course seemingly using two different voltage oscillators which will be fighting against each other phase wise if they are different frequencies and voltages. But even if they are the same frequency they are not likely to be 100% identical. The FPU would basically get a garbage clock. The setup may survive a brief period but they could ultimately damage something.


BTW this is the current setup which is stable.


Still does not work at 50MHz. The voltage does drop a little bit because of the faster oscillator and termination.

But it is not exactly a good method. Really the FPU needs to be on its own clock.

exxos wrote: 17 Nov 2022 10:40 The setup may survive a brief period but they could ultimately damage something.

Yeah, that was what I thought. OK, I won't recommend that. :P

BTW this is the current setup which is stable.

IMG_0255.JPG

Still does not work at 50MHz. The voltage does drop a little bit because of the faster oscillator and termination.

But it is not exactly a good method. Really the FPU needs to be on its own clock.

OK, I'll put that in the bank for future reference. I don't have caps to ground on the oscillator output ATM.

I presume you've either disabled FPUCLK in the firmware or you've removed R18 to get that to work?

Next test would be transferring that oscillator to the FPU OSC position and using a 50 on the CPU, I assume?

BW

Badwolf wrote: 17 Nov 2022 10:46 I presume you've either disabled FPUCLK in the firmware or you've removed R18 to get that to work?

I removed R18.

Badwolf wrote: 17 Nov 2022 10:46 Next test would be transferring that oscillator to the FPU OSC position and using a 50 on the CPU, I assume?

I want to try the 50MHz OSC on the FPU directly next.