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Yep. I need to build up a new board :(
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assign BUS_FREE = ({D[15:15]} != 16'b1);That sets wire BUS_FREE to be high when the single line D15 is anything other than binary "0000000000000001" and low when it is.exxos wrote: 05 Apr 2021 11:53Yep. I need to build up a new board :(
BTW, does this do what I think it does ? :lol:
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assign BUS_FREE = ({D[15:15]} != 16'b1);
dammit!! :lol:Badwolf wrote: 05 Apr 2021 12:40 That sets wire BUS_FREE to be high when the single line D15 is anything other than binary "0000000000000001" and low when it is.
So I'd guess not! :lol:
What are you trying to do?
Surprised the compiler doesnt spit the dummy at that...exxos wrote: 05 Apr 2021 11:53 BTW, does this do what I think it does ? :lol:
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assign BUS_FREE = ({D[15:15]} != 16'b1);
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assign BUS_FREE = ~D[15];oh thanks, that makes much more sense!
I still don't think that does what you want. D15 doesn't have a pull-up (does it?) and all this does is check if it's high.
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wire ST_BUS_ALL_HIGH;
assign ST_BUS_ALL_HIGH = ~&D[31:16]; // active low
I have looked at that site a lot but might as well be in Chinese. Pages of how stuff works doesn't really help when you have a specific problem and no example on how to do it. Even after spending hours looking around the Internet for solutions all I really come across is arguments on multiple ways of doing something which I think should be relatively simple. I'm sure that site explains things very well, but which of the hundred pages actually has an example of what I actually want to do on it, there is absolutely no way a novice like myself to know such things.terriblefire wrote: 05 Apr 2021 13:03 Spend half an hour reading this
http://www.asic-world.com/verilog/verilog_one_day.html
I just realised it is the upper bits which are actually on the ST bus D16-D31 on the CPU :roll:Badwolf wrote: 05 Apr 2021 13:10 I think you're meaning to check if the ST's bus has been pulled high?
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assign BUS_FREE = ~&D[31:16];
FDCP ff_dtack3r( .D( BUS_FREE ), .C( CLK100M ), .PRE( AS30 ), .CLR( 1'b0 ), .Q( ram_delay3 ) );
wire ram_access = ram_decode | ram_delay3;