exxos's Atari, Amiga & retro forum

See previous post. It looks very good. Never seen it before.

The problem with cycle accurate CPUs is that is not what you want for new accelerators. You don't want a 13-cycle multiplier/divider you want all instructions to be single cycle (like TG68K DotC)

alexh wrote: 21 Sep 2026 14:36 See previous post. It looks very good. Never seen it before.

First commit is from Jul 4, 2026 so I not checked in the meantime.

Still, nice to find such projects, obviously also coded using AI (perfect use case).

alexh wrote: 21 Sep 2026 14:36 The problem with cycle accurate CPUs is that is not what you want for new accelerators. You don't want a 13-cycle multiplier/divider you want all instructions to be single cycle (like TG68K DotC)

Then go for the 68060's integer multiplier :) Or the VIA Nano 3000.

Have all these cores actually been tested on real hardware ? As it mentioned Claude as contributor, you can probably knock out loads of cores in a week. Doesn't mean to say they work..

Both have reference hardware implementation for validation :

https://github.com/mattuna15/68881-fpga#validation-pcb

https://github.com/harrowm/mackerel_030f

And they claim to have been simulated with a quality test-bench. I've not tried either but there is a lot of polish here. I'm seeing all the right stuff. And the HDL doesn't look too much like AI code.

Obviously the commits say otherwise. But in the end it's the result that "counts"...

68040, sort-of :

https://github.com/apolkosnik/AP68040

Now there's only the 68060 remaining to complete the family.