exxos's Atari, Amiga & retro forum

Some games really benefit from the speedup:


And some become instant "hard mode" :lol:



I tried a bunch of games and contrary to what I would have guessed the majority didn't actually suffer from becoming unplayably fast so I think it's worth it to tidy this up into a proper feature.

It needs a bit of cleanup in the firmware, the ability to enable/disable from software, and as a first pass have a look at making the software side update cache after file i/o for those that are using floppy or acsi drives.
It's all in a rather quick and dirty proof-of-concept stage at the moment :D

Castle master ;)

Steve wrote: 08 Dec 2020 14:40 More work of genius from the great @agranlund :D Whatever will he do next? World peace? Free energy?

Hahaha :lol:
Thank you :) Maybe if more people played Atari we would one day achieve world peace!

I must admit, I did have a quick look into a similar performance speedup (for TT rather than TF though).

Basically, I concluded that the Shifter RAM needed relocating before anything really useful speed-wise could be done. :lol:

Im currently using a Shadow TT RAM system for copy/transform operations of screen data.

However, you are taking a different direction here with OS call (+ possibly MMU) relocations for speedups and I will be very interested in what you come up with.

Keep up the good work! :dualthumbup:

@agranlund Frontbench time ? ;)

So this is a custom firmware for the tf536 (regular edition) ? I wouldn't mind having this enabled for my H5 tf536 because it runs from IDE & doesn't need blitter.

Steve wrote: 13 Apr 2022 16:27 So this is a custom firmware for the tf536 (regular edition) ? I wouldn't mind having this enabled for my H5 tf536 because it runs from IDE & doesn't need blitter.

Yep. It's for the regular edition.
I eventually abandoned that particular path I wrote about before in the thread, but there is a firmware (and new maprom) which enables the L1 cache for ST-RAM - this attempts to solve the same thing but in a different way.
It isn't as big of a speed boost for ST-RAM programs as some of the earlier and more complicated experiments, but for the simplicity I think it works surprisingly well and it can make quite a difference for games running from ST-RAM.

There is before and after videos here:
https://www.exxosforum.co.uk/forum/viewt ... 318#p83155

And the firmware + new maprom program can be found here:
https://www.exxosforum.co.uk/forum/viewt ... =30#p83177

You may or may not have issues in TOS206, especially with Floppy and maybe other DMA devices. Turning cache off may help in that case.
Some programs may not work at all with cache enabled, some may run to fast etc..
Disabling the cache option in the Tos menu should help in that case.
I've ran a bunch of games but I don't want to say it's very well tested and I can't tell for sure how it effects overall compatibility.

Its a shame SRAM doesn't have a clear pin :( I was thinking about this the other day . I mean writing to a shadow ram and reading from it is doable as proven. Problem is it needs a 1 extra bit per address to tell if the shadow ram as been written to so we know it has valid data. On a bus master access it would need to clear the whole bank of that extra bit. Not possible with SRAM :(

If however we could fit like 50 million flip flops into a PLD I think it would actually be possible to cache the whole ST RAM area.. Within alt-ram. Simple idea, but doable not so much :roll:

agranlund wrote: 08 Dec 2020 00:38 I'm planning on investigating if I got all relevant signals available for snooping those DMA writes.

You need the DMA signal that goes from GLUE to MMU. You also need the databus, of course. And you also need to snoop writes to the DMA address registers.

exxos wrote: 13 Apr 2022 18:14 Its a shame SRAM doesn't have a clear pin :( I was thinking about this the other day . I mean writing to a shadow ram and reading from it is doable as proven. Problem is it needs a 1 extra bit per address to tell if the shadow ram as been written to so we know it has valid data. On a bus master access it would need to clear the whole bank of that extra bit. Not possible with SRAM :(

If you snoop bus maters access you never need to invalidate the shadow ram. It is always valid.

ijor wrote: 19 Apr 2022 22:51 If you snoop bus maters access you never need to invalidate the shadow ram. It is always valid.

Yep, Was talking to @Badwolf about just that a few weeks back. Time is never on anyone's side, unfortunately.