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Re: TF536 and H4 Benchmark

Posted: 13 Feb 2022 23:49
by exxos
TF536 ST edition - MAPROM1.8E - TOS206

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Re: TF536 and H4 Benchmark

Posted: 14 Feb 2022 08:15
by Cyprian
Interesting figures.

I wonder why the best results are with Instruction Cache Off. - D ON, I OFF

Re: TF536 and H4 Benchmark

Posted: 14 Feb 2022 10:31
by exxos
Cyprian wrote: 14 Feb 2022 08:15 Interesting figures.

I wonder why the best results are with Instruction Cache Off. - D ON, I OFF
No idea. But IIRC on the falcon the data cache on made the tests about 3% slower. So caches don't always help.

Re: TF536 and H4 Benchmark

Posted: 14 Feb 2022 13:48
by alexh
Cyprian wrote: 14 Feb 2022 08:15 I wonder why the best results are with Instruction Cache Off. - D ON, I OFF
Cache line fills from DRAM take more time than a single instruction fetch. Even with 030 burst mode. That time is usually made up when the CPU executes the full line from CACHE and doesn't read from DRAM. If the CPU doesn't execute a full cache line, perhaps due to branching, then the benefit of the cache is reduced. Even more so if that cache line becomes invalidated and re-filled due to code alignment. (Sometimes called cache thrashing) So depending on the code, iCache performance can be worse than no iCache.

Re: TF536 and H4 Benchmark

Posted: 19 Feb 2022 00:16
by exxos