BLITTER RE-CREATION THOUGHTS

[Smonson]

Hi, sorry I haven't read the complete thread but I see you're looking for bidirectional 3.3 to 5v interface logic - the one I used for the data bus on the HDMI thing is 74ALVC164245DL,112. It has two groups of 8 pins with a direction control and tristate pin per group. They're about $2 each in x10 pricing from mouser. I've had no problems with that one.

[exxos]

Hi, sorry I haven't read the complete thread but I see you're looking for bidirectional 3.3 to 5v interface logic - the one I used for the data bus on the HDMI thing is 74ALVC164245DL,112. It has two groups of 8 pins with a direction control and tristate pin per group. They're about $2 each in x10 pricing from mouser. I've had no problems with that one.

Problem is tri-state the buffers, when the FPGA goes tri-state, nothing is driving the buffers, so logic output to the bus will be "random"... The buffers need to be isolated, but there is no control for that. So I can't use "normal" buffers ICs.. only FET based ones which don't have tri-state issues or need for direction pin.

[Smonson]

Problem is tri-state the buffers, when the FPGA goes tri-state, nothing is driving the buffers, so logic output to the bus will be "random"... The buffers need to be isolated, but there is no control for that. So I can't use "normal" buffers ICs.. only FET based ones which don't have tri-state issues or need for direction pin.

You would need to change the direction of the buffer (or turn it off) at the same time that you tri-state the FPGA pins.

[Stimpy]

I've used an IDT part in the past, for floppy etc but can't remember which one.it was bidirectional. However the TI parts have very good documentation, so might be better choice. Most seem to be based on the MOSFET idea, which I've also used in discrete form for I2c etc.

Perhaps my old post wasn't clear, but with all suska cores you choose if you want your buffers internal or drive external ones. There are two top files in the hierarchy. You dont need to modify anything apart from your pin constraints file to put signals on your pin of choice.

[exxos]

Perhaps my old post wasn't clear, but with all suska cores you choose if you want your buffers internal or drive external ones. There are two top files in the hierarchy. You dont need to modify anything apart from your pin constraints file to put signals on your pin of choice.

So are you saying there is a top file which can tristate external buffers ? I don't know anything about FPGA so what you saying doesnt mean a lot to me. :(

[Stimpy]

Perhaps my old post wasn't clear, but with all suska cores you choose if you want your buffers internal or drive external ones. There are two top files in the hierarchy. You dont need to modify anything apart from your pin constraints file to put signals on your pin of choice.

So are you saying there is a top file which can tristate external buffers ? I don't know anything about FPGA so what you saying doesnt mean a lot to me. :(

Yes, I don't know how you would build it without choosing the right top file as they would otherwise conflict. If you use the SOC top file (designed for multiple cores in one FPGA) it gives you separate ports for everything.

FPGA do not support highz internally, just 1s and 0s. Only place you can use highz (Z) is on and external pin.

Constraints file for one thing allows you to move pins around, with certain restrictions. Some pins are dedicated to clocks etc.

The VHDL is very well written so if you want to learn a bit, having a read through a top file would be a good start.

[exxos]

Only just got home, but tried the hobbytronics board and works as expected... 3.3V one side, 5V other side, nothing screwing going on at all with that.

IMG_3353.JPG

[exxos]

This is the TXB0108 based board..

This acts even odder than the IDT chip...

3.3V one side, 5V other side... 0V 5V side and get 2.5V on the 3.3V side.... 0V the 3.3V side and get 3.27V on the 5V side...

This all makes no sense to me at all. I can't see I am doing anything wrong with these things, I mean the simple mosfet one works fine, but neither the Texas or IDT part function how they should... Really these chips should operate just like the single mosfet board. :shrug:

Will have another look tomorrow, but I think I am just going to avoid these chips... Will have a look at the suska code and see if I can see any other pins in the files...

wayyy back I got this https://www.exxosforum.co.uk/forum/viewt ... t=79#p5134 So will see if there is some other file which is different...

IMG_3354.JPG

[exxos]

OK so in wf101643ip_top_soc.vhd


I see BUSCTRL_EN : out std_logic;


Looks like I compiled wf101643ip_top.vhd before which didn't have the EN pin...

But some other differences as well :shrug:

Looks like separate pins for buses, in and out.. not sure why... That could double the amount of routing ?! It doesn't look so simple somehow... but maybe will just think about doing a mosfet adapter pcb.. or just make the adapters a little larger to fit all the mosfets.. not pretty, but it would work.

11111111.JPG

[exxos]

Looking though the files, I can only see this for BUSCTRL_EN

222222222.jpg

So maybe I just need to declare the pin to use it as that file looks like its part of the core stuff anyway...

I have emailed wolfgang to see if he understands about adding the missing signal....