BLITTER RE-CREATION THOUGHTS

Progress on our FPGA cores.
Post Reply
User avatar
exxos
Site Admin
Site Admin
Posts: 24239
Joined: Wed Aug 16, 2017 11:19 pm
Location: UK
Contact:

Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

So I gave up and started using 4 layers. Problem is with 0V,5V,3.3V,4.2V rails spanning everywhere, plus the routing for the buffers and FPGA, its just not possible to route on 2 layers. It was just ending up with loads of broken polygons everywhere.. but still.. its a small board so 4 layers isn't to bad.

aaa.jpg
aaa.jpg (112.52 KiB) Viewed 4913 times
https://www.exxosforum.co.uk/atari/ All my hardware guides - mods - games - STOS
https://www.exxosforum.co.uk/atari/store2/ - All my hardware mods for sale - Please help support by making a purchase.
viewtopic.php?f=17&t=1585 Have you done the Mandatory Fixes ?
Just because a lot of people agree on something, doesn't make it a fact. ~exxos ~
People should find solutions to problems, not find problems with solutions.
User avatar
exxos
Site Admin
Site Admin
Posts: 24239
Joined: Wed Aug 16, 2017 11:19 pm
Location: UK
Contact:

Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

Still at it :roll:

Only room for 4 caps in the corners, but think that be fine anyway. Simply no room for any more tracks or vias to link to other layers even now! Regulator slap-bang center, dedicated gnd layer and a poly fill gnd on bottom. 5V ended up on its own layer.

Will add the caps tomorrow, bum gone numb :)

1.jpg
1.jpg (140.27 KiB) Viewed 4900 times
https://www.exxosforum.co.uk/atari/ All my hardware guides - mods - games - STOS
https://www.exxosforum.co.uk/atari/store2/ - All my hardware mods for sale - Please help support by making a purchase.
viewtopic.php?f=17&t=1585 Have you done the Mandatory Fixes ?
Just because a lot of people agree on something, doesn't make it a fact. ~exxos ~
People should find solutions to problems, not find problems with solutions.
User avatar
rpineau
Posts: 534
Joined: Thu Aug 17, 2017 6:08 pm
Location: USA
Contact:

Re: BLITTER RE-CREATION THOUGHTS

Post by rpineau »

you have a short (orange circle) :
short.png
short.png (1.08 MiB) Viewed 4896 times
and the via just above that circle seem to touch the pad above it (in addition to the pin it's connection to).
Working ones : MegaSTE (68020) / TT030 / Falcon with AB040 & Eclipse / 1040STF
Need testing : Falcon with CT2
User avatar
rpineau
Posts: 534
Joined: Thu Aug 17, 2017 6:08 pm
Location: USA
Contact:

Re: BLITTER RE-CREATION THOUGHTS

Post by rpineau »

more potential issues (not sure if their are intentional as it's hard to read the signal names) :
short.png
short.png (1.08 MiB) Viewed 4894 times
Working ones : MegaSTE (68020) / TT030 / Falcon with AB040 & Eclipse / 1040STF
Need testing : Falcon with CT2
User avatar
exxos
Site Admin
Site Admin
Posts: 24239
Joined: Wed Aug 16, 2017 11:19 pm
Location: UK
Contact:

Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

rpineau wrote: Mon Sep 10, 2018 10:17 pm more potential issues (not sure if their are intentional as it's hard to read the signal names) :
A lot is very close, I've not run DRC yet :) I need to add JTAG tracks on yet as well..

EDIT:

ahh, thats a recent lot of issues as I moved the IC's a couple mm towards the edge, so not cleaned up those parts yet :)

The left one is to close.. the other orange circles are gnd via and gnd tracks :) I will send you the file to check when finished ;)
https://www.exxosforum.co.uk/atari/ All my hardware guides - mods - games - STOS
https://www.exxosforum.co.uk/atari/store2/ - All my hardware mods for sale - Please help support by making a purchase.
viewtopic.php?f=17&t=1585 Have you done the Mandatory Fixes ?
Just because a lot of people agree on something, doesn't make it a fact. ~exxos ~
People should find solutions to problems, not find problems with solutions.
User avatar
rpineau
Posts: 534
Joined: Thu Aug 17, 2017 6:08 pm
Location: USA
Contact:

Re: BLITTER RE-CREATION THOUGHTS

Post by rpineau »

No problem. I'll wait for the final files :D
Working ones : MegaSTE (68020) / TT030 / Falcon with AB040 & Eclipse / 1040STF
Need testing : Falcon with CT2
User avatar
exxos
Site Admin
Site Admin
Posts: 24239
Joined: Wed Aug 16, 2017 11:19 pm
Location: UK
Contact:

Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

Been routing most of today again.. got the caps on now. Had to go with 0603's are wasn't room for 0805 easily :(

Rodolphe will be happy with the JTAG header... Had a bit of trouble squashing it all in.. but managed it.

Image isn't with "filled" areas shown.

1.png
1.png (107.18 KiB) Viewed 4829 times
https://www.exxosforum.co.uk/atari/ All my hardware guides - mods - games - STOS
https://www.exxosforum.co.uk/atari/store2/ - All my hardware mods for sale - Please help support by making a purchase.
viewtopic.php?f=17&t=1585 Have you done the Mandatory Fixes ?
Just because a lot of people agree on something, doesn't make it a fact. ~exxos ~
People should find solutions to problems, not find problems with solutions.
User avatar
exxos
Site Admin
Site Admin
Posts: 24239
Joined: Wed Aug 16, 2017 11:19 pm
Location: UK
Contact:

Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

After talking to Rodolphe we realise that the suska code won't play nice with external buffers :roll:

Wolfgang says the blitter is a "drop in replacement" which it is, BUT, only if using a 5V FPGA, which doesn't exist. Which means using external buffers is the way to go, BUT, suska blitter doesn't output any signals to control external buffers, so this has put a huge spanner in the works :roll: I have asked TerribleFire if he can make sense of the code and patch it to work with external buffers.. So waiting to see if anything happens there.

One new problem is the address bus and databus need to be on their own IO buffer.. Currently there are 4 data pins on a address buffer chip, thats just how the pins are arranged on the blitter. So re-routing 4 lines means there would have to be another IO buffer, to which, there isn't any room left on the PCB :(

One main problem is while the FPGA blitter code sets the bus high-z, it can still read from the bus, which it needs for CPU > blitter access for example. So can't just simply tri-state the buffers to match what the FPGA does. So it actually rules out any sort of IC to do this job.

The code could set the pins to logic 1, as the buffers are actually turned off in that case, and 5V side is pulled high with MB pull ups.. then then blitter couldn't read from bus as all pins would be high.

Really each IO pins needs to be on its own "buffer", the only way to do that is with a resistor network and possible diodes. Though thats a bit daft to have 100's of resistors and diodes on the board.

The only way it would work , is to re-design the pcb, make it larger, and fix the code. Or try and find some FPGA which runs on 3.3V with 5V IO capability, which then means more work trying to figure out a new chip. The 5V capable devices which I found so far are really expensive, so not worth £60 for a blitter. So the project has hit a brick wall and I don't know what the solution is :(

I'm going to run some simulations on the mosfet buffer, to see if high-z on the 3.3V line would upset anything.. I dont see how it can though...
https://www.exxosforum.co.uk/atari/ All my hardware guides - mods - games - STOS
https://www.exxosforum.co.uk/atari/store2/ - All my hardware mods for sale - Please help support by making a purchase.
viewtopic.php?f=17&t=1585 Have you done the Mandatory Fixes ?
Just because a lot of people agree on something, doesn't make it a fact. ~exxos ~
People should find solutions to problems, not find problems with solutions.
User avatar
exxos
Site Admin
Site Admin
Posts: 24239
Joined: Wed Aug 16, 2017 11:19 pm
Location: UK
Contact:

Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

I put together a quick simulation circuit...

1.JPG
1.JPG (40.13 KiB) Viewed 4748 times

On the 5V side I connected to 0V, so the 3.3V site is also 0V.

If I connected 3.3V to 0V, then the 5V side is also 0V.

Should either side go high, the MOSFET is actually turned off and depends on the pullups to get the logic high. So at this point the input and output are actually isolated.

In terms of the FPGA 3.3V side going high-z, R1 will pull-up 3.3V to logic HI, and the 5V section would also be high. If the 5V site goes low, then the 3.3V side will also goes low.

So unless I am missing something, they should actually be no reason to isolate the buffers as the only time anything actually passes through is on a logic low level.

My only slight concern is that the 3.3V side in terms of the buffer, may not have a internal pull up.. So the state of the 3.3V line would actually be unknown.. As long as it is not 0V, it should not matter anyway... I will see if I can get a answer from IDT about leaving the 3.3V side is connected.. It should not really be a problem I think..

EDIT:

Also a simple explanation here.. http://www.hobbytronics.co.uk/mosfet-vo ... -converter
https://www.exxosforum.co.uk/atari/ All my hardware guides - mods - games - STOS
https://www.exxosforum.co.uk/atari/store2/ - All my hardware mods for sale - Please help support by making a purchase.
viewtopic.php?f=17&t=1585 Have you done the Mandatory Fixes ?
Just because a lot of people agree on something, doesn't make it a fact. ~exxos ~
People should find solutions to problems, not find problems with solutions.
User avatar
rpineau
Posts: 534
Joined: Thu Aug 17, 2017 6:08 pm
Location: USA
Contact:

Re: BLITTER RE-CREATION THOUGHTS

Post by rpineau »

For the pull-up I found this in the datasheet :
Internal Weak Pull-Up Resistor:
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.

So you should be good to go :)
Rodolphe
Working ones : MegaSTE (68020) / TT030 / Falcon with AB040 & Eclipse / 1040STF
Need testing : Falcon with CT2
Post Reply

Return to “FPGA DEVELOPMENT”