FPGA Blitter cycle exact core running now on an H5 motherboard:

- Blitter FPGA core on H5
- 20241020_180906.jpg (580.65 KiB) Viewed 154 times
This was using the same Qmtech FPGA board and adapters described in this MMU thread:
viewtopic.php?f=80&t=7312
The core itself has been already tested by
@Icky using his "Sparkalaphobia" board on an original STFM computer (See his post #95868 on this thread). Even when that board used a different FPGA (MAX10 vs Cyclone IV), I expected the port to be quite simple, almost trivial. It worked, but some tests didn't show 100% accuracy and it wasn't easy to find out what was going on.
You might remember that the exact Blitter timing in some circumstances depends on the pull up on the BGACK line. A weaker pull-up might produce, again, in some cases, a slower timing. See this thread for details:
viewtopic.php?f=29&t=6030&start=30
I was, obviously, well aware about that. I knew that the results on this H5 might be different to the results on other computers depending on the pull up installed in this board. But on the very same computer, the FPGA core and the original Blitter should get exactly the same timing. But they didn't, my core behaved slower.
This H5 board has a weak pull-up. So the test posted in the thread mentioned above gave the slower result with the original Blitter:

- Blitter test with weak pull up on BGACK
- 20241020_180433.jpg (364.25 KiB) Viewed 154 times
So far so good, that was expected. But my core gave a different, even slower, result:

- Blitter test with very weak pull up or large capacitance
- 20241017_105633.jpg (338.38 KiB) Viewed 154 times
After many tests I realized that I measured the pull-up wrong before. It is even weaker. It's a 4.7K pull up as as standard on the ST. This still doesn't explain why the result is different than with the original Blitter. Well, the difference wasn't the core vs the original chip. The difference was that I was testing the core with a logic analyzer attached for diagnosis. And it seems that this was enough to produce an extra load on the signal that made the BGACK raising edge even slower. And as a matter of fact, when I tested the original Blitter with the LA still attached, I do get the same (slow) results!
To solve the pull up mess for good, I implemented special logic in the core to "ignore" the on board pull up and and a configurable option to select the exact BGACK timing. Now it can behave and produce the same timing as if there was a stronger or weaker pull up, independently of the actual pull up fitted on the motherboard.