BLITTER RE-CREATION THOUGHTS

[keli]

plus what is inside each block...

We could reimplement the blitter using 74x series chips!!! :P It'll be HUGE!

[exxos]

We could reimplement the blitter using 74x series chips!!! :P It'll be HUGE!

Yeah, you can do that :)

[slingshot]

Hi!

I also interested in this work. Actually I did the GSTMCU already, by translating the schematics into Verilog. I suggest to do the same, and don't bother with schematics drawing in Quartus.
The negative clock for the cells can be ignored in upper levels, it just needed to make the module work with the ASIC-vendor's basic cells.

[exxos]

I also interested in this work. Actually I did the GSTMCU already, by translating the schematics into Verilog. I suggest to do the same, and don't bother with schematics drawing in Quartus.

Interesting, must have been huge work ?

Well we don't have any programmers to do such work, so gate per gate is only option for us. We used suska cores, but it doesn't work correctly at 8MHz and nobody offer to help fix it. It is why we copy schematics over so it can be compatible as original blitter.

[slingshot]

I also interested in this work. Actually I did the GSTMCU already, by translating the schematics into Verilog. I suggest to do the same, and don't bother with schematics drawing in Quartus.

Interesting, must have been huge work ?

Well we don't have any programmers to do such work, so gate per gate is only option for us. We used suska cores, but it doesn't work correctly at 8MHz and nobody offer to help fix it. It is why we copy schematics over so it can be compatible as original blitter.

Was some months :)
Actually the schematics cannot be used 1:1 in an FPGA: there are lot of asynchronous logic in them (e.g. a signal used as a clock in another flip-flop). This won't synthesize correctly in every case (you need luck...). However the async logic itself can be a base to run the design in a simulator. I don't think any simulator will run the schematic-level translation, and at the end you'll need to do all the debugging in hardware (you don't want that).
My work is public (actually a base of a MiST core), you can found it here:
https://github.com/gyurco/gstmcu
Some signals are still missing to make a true replacement of the original chip (but it's not hard to add them, just that wasn't the goal).

[exxos]

Thanks, it could be a possible option for the future. Though we need to replicate & test the original ST chipset before looking at STE chips.

[slingshot]

Thanks, it could be a possible option for the future. Though we need to replicate & test the original ST chipset before looking at STE chips.

Unfortunately there are no public schematics about the original chipset (however the GSTMCU can be split to Glue and MMU if needed - I implemented an ST/STe switch into it, but some differences between the two modes are still not done, as I don't know about them 100%).

[exxos]

Unfortunately there are no public schematics about the original chipset (however the GSTMCU can be split to Glue and MMU if needed - I implemented an ST/STe switch into it, but some differences between the two modes are still not done, as I don't know about them 100%).

Yeah schematics are not there for other chips. We have suska code, which isn't ideal. But could you create a ST blitter core ? We have board made up running suska core already, but its only running at about 25% speed because it expects 32MHz RAM access for some odd reason.

[slingshot]

Yeah schematics are not there for other chips. We hae suska code, which isn't ideal. But could you create a ST blitter core ? We have board made up running suska core already, but its only running at about 25% speed because it expects 32MHz RAM access for some odd reason.

I studied Suska code a bit, but realized that it's not cycle-exact. Yeah, probably I can do the Blitter, too, but would take some another months...
32 MHz master clock is not a bad thing in a synchronous design: the clock enable signals must be 8MHz (actually what I also did with the GSTMCU). If I would do the blitter, I would do the same: 32 MHz master clock with a clock enable for the positive and the negative edge of the 8MHz clock (one positive and one negative clock enable in every 4th 32MHz tick). This surely would require to wire up the ST's 32MHz master clock, too into the replacement board, but I don't see any problem with that.
Using the original 8MHz clock would require to write logic for both positive and negative edge (as I see on the schematics, both are used by design - and not because of the dual-clock requirement of some cells). And also the asynchronous design couldn't be exchanged with a completely synchronous one.

[exxos]

I studied Suska code a bit, but realized that it's not cycle-exact. Yeah, probably I can do the Blitter, too, but would take some another months...
32 MHz master clock is not a bad thing in a synchronous design: the clock enable signals must be 8MHz (actually what I also did with the GSTMCU). If I would do the blitter...

The ST 32MHz we tried with Suska blitter and it malfunction really badly. https://www.exxosforum.co.uk/forum/viewt ... 220#p27218 But the ST's 32MHz clock isn't very strong, it cannot really drive anything other than shifter.. but thats a lot of other problems which I won't go into here.

Yeah time is a problem for everyone. I think we will have the blitter core copied into Quartus by the end of the year.. as to if we copy it correctly is another matter :)