BLITTER RE-CREATION THOUGHTS

[exxos]

Didn't work. As soon as you turned on the Blitter it froze.

Damn. Maybe we should bodge on a 32mhz osc into the shifter and run the same clock to the FPGA board ? It could just not like out of sync clocks...

[Icky]

Damn. Maybe we should bodge on a 32mhz osc into the shifter and run the same clock to the FPGA board ? It could just not like out of sync clocks...

Or I could mod my STF Remake Alpha to accept the FPGA Blitter and use the 16MHz mod to put everything back to stock 8MHz and feed the Blitter the 32MHz line.

[exxos]

Or I could mod my STF Remake Alpha to accept the FPGA Blitter and use the 16MHz mod to put everything back to stock 8MHz and feed the Blitter the 32MHz line.

Yeah, but sounds more work than bodging a osc onto the shifter...

[Icky]

Yeah, but sounds more work than bodging a osc onto the shifter...

True, haven't had my caffeine this morning. Although the FPGA board is 3.3v so will need a 5V <-> 3.3v buffer for that line.

[exxos]

True, haven't had my caffeine this morning. Although the FPGA board is 3.3v so will need a 5V <-> 3.3v buffer for that line.

You may find by the time the shifter is loaded, and go via a 33R that you may well end up with 3V output on it anyway.

[Icky]

True, haven't had my caffeine this morning. Although the FPGA board is 3.3v so will need a 5V <-> 3.3v buffer for that line.

You may find by the time the shifter is loaded, and go via a 33R that you may well end up with 3V output on it anyway.

I’ll take a look tonight :)

[Icky]

Just thought I would share some videos of the FPGA Blitter Board running using the stock code at different clock speeds and the effects it has.

Running @ 8MHz



Running @ 16MHz



Running @ 32MHz

[dhedberg]

Just thought I would share some videos of the FPGA Blitter Board running using the stock code at different clock speeds and the effects it has.

Running @ 8MHz
...
Running @ 16MHz
...
Running @ 32MHz
...

What about 64MHz? :lol:

[exxos]

What about 64MHz? :lol:

:chairsmack:

[exxos]

I have been looking at the schematics again today, and still confused over some of the logic.. For example..

ff.JPG

Sure its a FlipFlop, but why 2 clock inputs, They are just C and /C driven by a inverter elsewhere. Normally C would latch on the falling edge, and /C Would latch on the rising edge. But this one has both. I've noticed this funkyness all over with other blocks as well. I think only 1 clock is needed, but no way to know what edge its supposed to latch on :shrug: