Things are a lot easier with STFMs as you can swap bits about. Milan's not so simple :Pagranlund wrote: 22 Jun 2025 19:27 That’s a really cool board, going to be interesting to follow this blog. I hope you do get it running :)
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Fixing my Milan 040 (or not) blog
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Re: Fixing my Milan 040 (or not) blog
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Re: Fixing my Milan 040 (or not) blog
On the flash (not sure if its actually a boot ROM or TOS at this point ?!) Shows some activity on the first 3 address lines, D0 sends out a few pulses. No other data bits are doing anything (just stuck high)
Thats now the first problem.. how to find whats supposed to go in the chip.. how to program the thing..
Thats now the first problem.. how to find whats supposed to go in the chip.. how to program the thing..
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Re: Fixing my Milan 040 (or not) blog
That seems about normal actually.exxos wrote: 22 Jun 2025 19:28 It starts heating up form power up.
27c cold
30 seconds 32c
60 seconds 37c
1.5mins 40c
2mins 43c
Ok, probably if you tried 2 CPUs it's not the problem then :) It does have the advantage that it's hard to mash pins on the back :p
Maybe the damage is under the SIMM socket. If a short happened at the SIMM pins it would need to be mega-unlucky to short one of them against VCC but I suppose its possible. If that happened, the RAM interface silicon would be the next up the chain... seems a bit weird though?exxos wrote: 22 Jun 2025 19:28 Yeah, I don't see anything bashed anywhere. But when I first looked at it (20+ years ago) the outside simm socket looked damaged, hence why I changed it. So I assume the screwdriver hit that simm socket.
Does the reset circuit actually come out of reset after delay? I'd probably begin with that and then look at HALT/BERR and related, then the CS/BG related lines on different chips.exxos wrote: 22 Jun 2025 19:28 I checked and flash CE/OE goes low after pressing reset, stays low after that. So its pretty dead :(
If the memory/bus control was damaged it could affect the flash select as well.
Pity they are all soldered, although you could still lift individual legs to stop them hogging the bus one at a time.
One of the very sad facts about giant PLDs is the more stuff they have on them they less you can debug / divide up the problem if something is wrong... and if the FW is not public, you're stuck with a bespoke customchip you can never produce a working version of. :/
d:m:l
BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
YT: https://www.youtube.com/@dmlTPT
BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
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Re: Fixing my Milan 040 (or not) blog
Maybe. I did get a reply from Qwe earlier. He doesn't seem convinced a "scredriver" could kill something that easily.. but that is just what the original owner told me.. could be total BS...dml wrote: 22 Jun 2025 19:51 Maybe the damage is under the SIMM socket. If a short happened at the SIMM pins it would need to be mega-unlucky to short one of them against VCC but I suppose its possible. If that happened, the RAM interface silicon would be the next up the chain... seems a bit weird though?
I think reset works as right after I get some activity on the flash.exxos wrote: 22 Jun 2025 19:28 Does the reset circuit actually come out of reset after delay? I'd probably begin with that and then look at HALT/BERR and related, then the CS/BG related lines on different chips.
I found my programmer can read the flash..
Verified as the latest one here https://www.uweschneider.de/en/downloads.php
release_990708
So thats not dead at least..
So the question is why is only D0 pulsing at this point.. Problem is thats a "boot block" so I assume its not going to be booting TOS for some time later.. that makes it hard to tell anything.
I guess I could remove the CPU and hardwire for the address lines low to make things easier to diagnose on the databus.. But at this point don't really know what the databus is actually supposed to be doing..
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Re: Fixing my Milan 040 (or not) blog
Activity on D1, A0,A1,A2.. got bored testing more address lines but a few others like A12 also pulsing.
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Re: Fixing my Milan 040 (or not) blog
So it's not completely dead :p game on!
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BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
YT: https://www.youtube.com/@dmlTPT
BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
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Re: Fixing my Milan 040 (or not) blog
The Milan page says you need 16MB minimum and needs to be EDO for the machine to operate. I guess you have a 16MB simm in there?
In the first pic, the ISA slots look like they have green corroded bits. Hard to tell though the photo is blurry. You might also want to confirm the caps are ok and no tantalums etc. the usual stuff that stops things early before you get into signals.
In the first pic, the ISA slots look like they have green corroded bits. Hard to tell though the photo is blurry. You might also want to confirm the caps are ok and no tantalums etc. the usual stuff that stops things early before you get into signals.
d:m:l
BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
YT: https://www.youtube.com/@dmlTPT
BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
YT: https://www.youtube.com/@dmlTPT
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Re: Fixing my Milan 040 (or not) blog
Just 99% dead then :P
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Re: Fixing my Milan 040 (or not) blog
So long as its the 99% outside of the PLDs you're still winning :)
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BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
YT: https://www.youtube.com/@dmlTPT
BadMooD d/l: https://www.leonik.net/dml/sec_bm.py
SVO30 d/l: https://www.leonik.net/dml/sec_svo30.py
Q2 engine d/l: https://www.leonik.net/dml/sec_q2.py
AGT project: https://www.leonik.net/dml/sec_agt.py
Atari page: http://www.leonik.net/dml/sec_atari.py
YT: https://www.youtube.com/@dmlTPT
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Re: Fixing my Milan 040 (or not) blog
16MB 60ns, but doesn't say or not EDO.dml wrote: 22 Jun 2025 20:25 The Milan page says you need 16MB minimum and needs to be EDO for the machine to operate. I guess you have a 16MB simm in there?
Yeah it needs a bath. No caps look bad, but will double check later.In the first pic, the ISA slots look like they have green corroded bits. Hard to tell though the photo is blurry. You might also want to confirm the caps are ok and no tantalums etc. the usual stuff that stops things early before you get into signals.
Qwe said:
I don't think it gets far enough to get to beep codes..Here some word how the boot process works:
After power on the PLX loads it's configuration from a EEPROM.
Then the PLD executes a write to the PLX to set it into Busmaster mode.
The 040 requests the local bus and the 1032 grants it.
Then the 040 wants to get the reset vector.
The PLX translates the address and recognizes it's a PCI address and
requests the PCI bus.
The 1024 grants the PCI bus.
The ISA bridge recognizes the address on the PCI bus as a ISA address
and starts four 8-Bit ISA cycles to fetch the requested bytes. And
since it is a Flash address it also generates the chip select for the
Flash.
So the first thing to check is if you can see the CS signal at the
flash.
If yes, and you only see 8, the processor got a double bus fault and is
halted. Then the problem is the flash or one of the data lines.
If yes, and you see more than 8 cycles the processor is booting and you
should connect the speaker to listen for beep codes or plug a POST cart
into the ISA bus to see the post codes.
If no, you go up the chain, check if the PCI bus was granted, the
processor bus was granted etc.
I sent a email to Uwe asking of my flash sounds normal.. but only D0 toggling sounds stange. But if that is the problem, 7 stuck high databits somewhere isn't going to be pretty unless its the CPU..
I guess I could remove the CPU, try forcing other databits low via a 1K resistor to see if they change or not..
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