Trying to reverse engineer the William Stuart Systems ZX81 sound card.

[ijor]

However, the address decode logic is completely perplexing. How on Earth do you do address decoding using NOR gates?

Yes, why not? A NOR gate has the same functionality as an AND gate, just inverted. There is even a theorem about that. Check "De Morgan's" law.

Using NOR and NAND gates was very common because they are faster, and usually cheaper, than non inverting gates. A NOR gate is particularly handy when you have to deal with low active signals. Also inverted outputs have zero cost when you have to combine several gates anyway, because multiple inversions compensate each other.

Just build a truth table. A truth table would tell you which input combination asserts the output signals.

Well, the F series chips arrived and...

I wouldn't change the logic family blindly without any specific reason. Faster is not always better. Sometimes it is even worse. Does the card work with LS chips and it works fine? Then why change it unless you have a good reason.

If you want to be precise, then you have to perform a comprehensive timing analysis.

[stephen_usher]

Well, the F series chips arrived and...

I wouldn't change the logic family blindly without any specific reason. Faster is not always better. Sometimes it is even worse. Does the card work with LS chips and it works fine? Then why change it unless you have a good reason.

If you want to be precise, then you have to perform a comprehensive timing analysis.

The problem is that the AY-3-8910 works in a fundamentally different way to the Z80, latching the data *AFTER* the Z80's write cycle has completed and so there's a hope that the AY latches the data before the bus changes. Using the F series logic chip makes the transition quicker making it more likely that the AY will latch the data in time. I could show by delaying certain signals that the probability of the AY reading the correct values got worse.

Switching to the F series logic for the BC1(? can't remember, could be BC2) signal allowed the AY to correctly read the data *IF* I made the AY A9 input asserted all the time, but not otherwise.

[ijor]

The problem is that the AY-3-8910 works in a fundamentally different way to the Z80, latching the data *AFTER* the Z80's write cycle has completed and so there's a hope that the AY latches the data before the bus changes.

I'm not an expert on the Z80 architecture, but I suspect it is the same with any other peripheral. Peripherals at the time weren't usually fast enough to latch the data at the start of the write cycle, if the Z80 allowed that at all by providing enough setup time before the write edge, which I'm not sure.

But the main point here is, how this board worked originally? Or this board didn't actually work at the time, or it was problematic, or what?

Using the F series logic chip makes the transition quicker making it more likely that the AY will latch the data in time. I could show by delaying certain signals that the probability of the AY reading the correct values got worse.

Switching to the F series logic for the BC1(? can't remember, could be BC2) signal allowed the AY to correctly read the data *IF* I made the AY A9 input asserted all the time, but not otherwise.

Are you using the same Z80 cpu that the original machine used, or are you using, say, a more modern and faster Z80? That would explain the behavior because a faster CMOS part might provide less hold time.

[stephen_usher]

The problem is that the AY-3-8910 works in a fundamentally different way to the Z80, latching the data *AFTER* the Z80's write cycle has completed and so there's a hope that the AY latches the data before the bus changes.

I'm not an expert on the Z80 architecture, but I suspect it is the same with any other peripheral. Peripherals at the time weren't usually fast enough to latch the data at the start of the write cycle, if the Z80 allowed that at all by providing enough setup time before the write edge, which I'm not sure.

But the main point here is, how this board worked originally? Or this board didn't actually work at the time, or it was problematic, or what?

The AY-3-8910 was specifically designed as a support chip for a General Instruments CPU which controlled the chip directly and which only put the data onto the chip's data bus at the point where the select signals were deasserted. The data sheet specifically says that when used in other systems this must be emulated. i.e. the data must stay on the bus after the select lines have been deasserted. The data sheet says that this period is at least 100ns, and that the R/W line shouldn't change during this period either.

Looking at the logic analyser output on the ZX81 and this board the timing between BC1 going high and the R/W logic changing is at best just over 100ns, at worst around 70ns. So it's pot luck if the AY chip latches the data quick enough. A few ns is enough to make all the difference. I delayed BC1 by putting the signal through a an inverter twice and the board didn't work at all. That was only a small number of ns.

A correct design for this board would have a data latch in front of the AY chip to allow the sound chip to always have the correct value on the bus.

The original board probably worked by the maker selecting chips that happened to work. This wasn't unusual in the late 70s and early 80s where computer manufacturers stating in the service documentation that chips from a specific manufacturer had to be used and sometimes even stating the factory and date code ranges required.

Using the F series logic chip makes the transition quicker making it more likely that the AY will latch the data in time. I could show by delaying certain signals that the probability of the AY reading the correct values got worse.

Switching to the F series logic for the BC1(? can't remember, could be BC2) signal allowed the AY to correctly read the data *IF* I made the AY A9 input asserted all the time, but not otherwise.

Are you using the same Z80 cpu that the original machine used, or are you using, say, a more modern and faster Z80? That would explain the behavior because a faster CMOS part might provide less hold time.

The CPU is the original with a 1981 date code.

[ijor]

Hi,

Sorry for the delay ...

The AY-3-8910 was specifically designed as a support chip for a General Instruments CPU which controlled the chip directly and which only put the data onto the chip's data bus at the point where the select signals were deasserted. The data sheet specifically says that when used in other systems this must be emulated. i.e. the data must stay on the bus after the select lines have been deasserted.

This is true for just about any other peripheral chip. Evey single device based on latches or flip flops requires hold time. You will see the same requirement on any datasheet. Some require more hold time, other require less. But any sequential logic requires hold time. This is intrinsic to how a latch works.

Just for completeness ... Some devices might specify 0 hold time, or even negative hold time in some cases. But this is because the device internally buffers the data signals and that is enough to provide the hold time required by the latches.

The original board probably worked by the maker selecting chips that happened to work.

Possibly. But that would mean that even then it would fail in some systems. The manufacturer could control its own board, but it can't control the computer or the environment. If the timing is so strict, that would mean that a slightly slower system, which could perfectly happen depending on voltage and temperature, would fail.

[stephen_usher]

The original board probably worked by the maker selecting chips that happened to work.

Possibly. But that would mean that even then it would fail in some systems. The manufacturer could control its own board, but it can't control the computer or the environment. If the timing is so strict, that would means that a slightly slower system, which could perfectly happen depending on voltage and temperature, would fail.

Indeed... welcome to the fun of early home computers and peripherals.