JezC - the second (and laST) H5C1 build

[JezC]

I've connected up the 'scope so the 4 channels are monitoring Reset, AS, DTACK & ROM_CE.

Triggering on the rising edge of RESET, I can see 4 accesses where AS, DTACK & ROM_CE all go active but then a 5th where I only see AS, no ROM_CE or DTACK.

Is there a subset of the pins going to the GLUE that I can monitor to try and see which signal(s) is/are faulty?

[exxos]

I would take out the CPU and do these tests... viewtopic.php?p=29465#p29465

It sounds like its trying to read ROM but failing for some reason.

[JezC]

I would take out the CPU and do these tests... viewtopic.php?p=29465#p29465

It sounds like its trying to read ROM but failing for some reason.

Ok, thanks - will see if I can get that set up at some point in the next few days...

[JezC]

Had almost no time for retro hobbies in the last couple of weeks - might post about the reason in my general blog at some point (when I feel able to share...).

Just managed to sneak a few minutes on looking at the signals on this second H5C1 at boot to compare with the first H5C1...see below:

yellow = reset (68k expansion socket pin 18) - triggers on rising edge

green = AS (68k expansion socket pin 6)

blue = DTACK (68k expansion socket pin 10)

pink = ROM_CE (JP 13 pin 1 or 2 - which are shorted together by jumper link)

First H5C1 at boot - notice that I'm getting two rising edges on Reset (using the reset button for generating the reset)

h5_boots.png

Second H5C1 at boot - first image is the total activity, second is zoomed in on the first burst of activity.

h5_bo_0.png

h5_boot0.png

So, the behaviour of the two is very different (but maybe sort of matches the first bit of activity of the first H5C1 before the second reset???)
Is the extra reset signal on the first H5C1 normal?
I might have to get my H4 board set up to check on that (as that one boots & floppy etc. work OK)...

I will look at the general signals with the processor removed on the second H5C1 but didn't have time for this today...

[exxos]

If I remember rightly one of the first instructions run in TOS is a reset. I asked about that before. So the double rest is normal.

As your not getting the double reset, your not running ROM. Trying to run TOS206 would probably cause the same symptoms.

Again you need to remove the CPU and hardwire that H4 test. You may have a bad bit on the databus and you need to read back what the CPU is seeing from ROM.

[JezC]

If I remember rightly one of the first instructions run in TOS is a reset. I asked about that before. So the double rest is normal.

Thanks - good to know.
:thumbup:

As your not getting the double reset, your not running ROM. Trying to run TOS206 would probably cause the same symptoms.

Again you need to remove the CPU and hardwire that H4 test. You may have a bad bit on the databus and you need to read back what the CPU is seeing from ROM.

Yes, still planning to do this but like you time is often limited - this was a simple & relatively quick check to swap the EPROMs between the two H5C1 boards and see if anything changed (which it didn't - so I know the EPROMs are both working the same at least).
I also captured the scope images for future reference as I'll most likely forget what they looked like before I get the next chance to diagnose further...
:lol: :roll:

[exxos]

Ages ago I started this project viewtopic.php?f=18&t=1789&p=79088&hilit=led#p79088 but lack of time as normal...

But maybe I could do a simple version. Just hardwired the bus and has LEDs to output the databus in a small 68k footprint. It would help people troubleshooting a dead machine. Even original machines. But there probably isn't much demand for such a board anyway.

[JezC]

I have borrowed a logic analyser (Saleae Pro 16 or something like that) plus the scope I'm borrowing from work has a logic analyser capability so I just need to make the time to try something.

I do remember reading about that years ago, not surprised that you've had too many other projects in flight to stop you progressing that one...

I'll check what connections I can make to a socket or similar (or maybe even a DIP68k processor) to check the bus at/just after reset - maybe even tonight...

[JezC]

Well, didn't happen the other night....but I managed to do some checks (visual first, then with DMM) and after a bit of cleaning of a few tracks & tweaking the PLCCs in their sockets a bit, I now have it booting to the desktop!
:D

So, next I checked that was working a few times in succession (yes...) then powered off & connected the floppy drive.

That is recognised by the tweaked TOS 1.04 build...but as for my first H5C1 if I put a floppy in the drive, it bombs and then needs a reset to start it.

So, at least I've got both H5C1 boards to the same state.

Next step might well be to set up the H4 and monitor the signals around the floppy with & without a floppy in the drive & then compare those against the H5C1s...

Close, but no cigar.
:roll:

[exxos]

That is just so odd. Your not trying to use the osc and shifter input to the 1772 are you. If you not touched the solder jumper then all is good.

Thought you could try using the osc to rule out clock issues.