STE V1.5 32MHz BOOSTER - STATUS

Help & information about the STE V1 series boosters.
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

Just printed the revised spacer... You can just about see the gap between the plastic CPU.. So this just means the CPU as a bit of ventilation..

I printed it with PLA and ABS. I think the ABS is a fraction stronger so likely use that this part.
v2.jpg
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The booster is on test again without the ROM CE line connected.. It could be tripping up on ROM access (to fast)... The problem is the booster was re-seated while this was happening... So I will have to repeat the test probably several times to try make sure it is not bad connections or problems with ROM access.
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

Without ROM CE connected to the booster, its run for 30 loops, which is getting on for 2 hours.. so will reconnect CE and see what happens...

EDIT:

OK crashed after 13mins... So will investigate the ROM CE line... possible noise or the ROM is "slowing down" as it warms up.

EDIT2:

added another 68R in series with ROM CE (2x68R total now) Signal didn't look to bad anyway. Started the tests again, ROM access test gone back to 309% (was 368 I think before) but this does not actually affect the overall speeds of any tests..

EDIT3:
OK, that crashed as well.

Starting to think I am pushing the ROM speed to much with this thing.

I have put back in a booster which has the GAL in a socket, this one has a 38MHz osc... I will leave this running and see what point this fails that making any further changes to this board... I am thinking to add a small wait state onto the ROM access.

EDIT4:
This particular booster has run 10 loops so far... But I thought I would reprogram the GAL is to make sure it did not have some experimental firmware.. The tests of restarted..

I took out the extra 68R resistor in series with the ROM_CS line... Oddly this booster still only shows 309% on ROM access, despite this is using a 38MHz osc (was 36MHz on the other booster I was testing before).

As everything is identical other than the booster board itself now, this board is actually running slower than expected.. I can only assume that the GAL itself is adding delays.. I have documented before that 7ns GALs can actually be 10ns,15ns or 25ns parts.. But with China reprinting everything you never know what you are getting..

What I mean by running is lower is that ROM access 309% which should be 368%... Overall tests are a few percent higher due to the 38MHz osc.. There's nothing actually wrong here.. But obviously we have a drop in ROM access speeds.. Could be down to the different CPU... But I suspect this is down to GAL speeds.

This is probably why this problem is difficult to diagnose. As in some cases the CPU simply cannot run 40MHz.. But as the ROM access speed is in part down to delays in the GAL logic itself, this is in itself likely causing ROM access delays from 7ns to 25ns.. Where the slower GAL's likely working better than the faster ones.

This is the problem when you get to these sort of speeds as your literally down to the wire a few nanoseconds in the wrong place and the thing fails.. And as we are dealing with multiple hardware tolerances all the time, it is difficult to make the booster which will work in all cases.. Of course we have not actually considered some ROM chips may not overclock as well as other ones yet...

So what I will do is on solder the GAL on the previous 36 MHz booster, and reprogram the firmware to add in a wait state onto the ROM access and then retest it again..

It will be possible that some boosters may be slightly faster than others because of the delays on the GAL itself.. But I need to program these things with worst-case timings... Hopefully that will allow me to make some headroom in getting stable batches running...

EDIT5:

The 38MHz was running for 76mins loop 24... so powered off and trying the 36Mhz one again now the GAL is in a socket (I need to take a new base line figure to when it locks up, which is.... oh... 30 seconds then :lol: )
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by Maeke »

exxos wrote: Thu Nov 08, 2018 11:55 am Just printed the revised spacer... You can just about see the gap between the plastic CPU.. So this just means the CPU as a bit of ventilation..

I printed it with PLA and ABS. I think the ABS is a fraction stronger so likely use that this part.
I'd also suggest the abs one, it supports better heat than pla.
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

Further to my previous post which I have been updating throughout today..

I now have the 36MHz booster connected with one wait state on ROM access.. Basically this now is the same speed as the 32MHz booster with the exception that integer division is about 50% faster. This basically means a 25ns wait state on ROM access..

So will leave this testing again and see how far it gets... Hopefully it will not lock-up this time... But it does pose a bit of a issue that the ROM access really needs something like 10ns delay on it as standard :roll:

In actual fact from accesses 267% currently (should be 307%) ... So this booster actually does pretty well efficiency wise to equal 32MHz speeds for ROM access..
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

Next update...

Runtime 45 loops 155mins ( 3 hours pretty much) no issues.

I've put back the normal firmware (no waitstates)

I have added 50pf onto ROM_CE, and added back another 68R in series (136R total) ... In theory it should give about 10ns delay....

ROM tested at the same 269%... so seems correct... so removing a 68R should be about 6ns delay...ROM still at 267% :roll:

Now 68R and 25pF, ROM speed back up to 309%... Delay should be about 4ns...crazy...

So now back to testing to see if it will run for the next couple hours...

:stars: :stars: :stars:


So basically the ROM is maxing out at in effect 32MHz... I'm not really surprised about this, and I already documented on the previous booster that 32MHz is pushing the ROM past its limits to achieve that speed..

With these new tests, the CPU is running even faster, its pushing the timings even further. Simply into breaking point. Where after about an hour's run, things are just warming up and going out of tolerance by a couple of nanoseconds which is enough to cause problems.

So where does this leave everything ?

I need to try again 40MHz.. But will likely have to be tomorrow now.. But I really think the CPU itself is not running at that speed.. As I am pretty sure I tried it without ROM CE connected still failed. So the probable maximum speed of this booster is likely going to be 38MHz.

The clause here is that ROM access speed is a mixed bag. So likely a 25pF capacitor will have to be soldered on the ROM_CE line as standard (will likely do this on the back of the booster board). Then if some boosters are not stable or suffer similar problems of failing after machine warms up, then another 25pF will have to be added slow down the ROM access back down to in effect 32MHz.

:dizzy:


EDIT:

Bugger, that failed as well... so trying 50pF and back to 267% ROM access. We'll see if this works, which I think it should, as it is the same as adding the wait state like before (or very close to).

A possible option is that I do have a spare IO pin on the GAL.. I could program that pin to be used as a switch to enable wait states or not.. This way people can try it out on their individual machine rather than me trying to account for everything all at once.

Some people may get lucky and it may run at this speed, if it does not, the wait states will have to be enabled..

I think the problem here is that when I used the motherboards 32 MHz clock, I could time everything very precisely as everything was synchronised. But when we have a free running clock, even if it was still was 32 MHz, we actually introduce random delays between 0- 32ns. so this is then why we need additional delays on the ROM access as we have to account for best and worst timings. Which unfortunately means the ROM access is inherently slower.

But even though ROM access is showing at 267% instead of 307%, the tests overall will run actually faster because of the faster CPU clock of 38 MHz. No test is slower than the previous 32Mhz booster anyway.
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

Right, it is pretty conclusive now that the ROM simply cannot run faster than effectively 32MHz. But the main problem here is the decoding speed by the ST chipset for the ROM chip enable line.. So nothing I can do about that.

So by default the ROM access will have to have a wait state inserted. I will however see if I can tweak the firmware so this can be turned off, some people may get lucky and it may be stable for them.. But obviously I'm going to have to program these with a wait state as the default. I will try to do this with a jumper wire on the back of the GAL... For example wired to 5V is wait states enable, and wired to 0V is wait states disabled.

Once I have created the new firmware (assuming it can be done) I will revisit the 40MHz on this current board...
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by JezC »

exxos wrote: Fri Nov 09, 2018 2:08 pm Right, it is pretty conclusive now that the ROM simply cannot run faster than effectively 32MHz. But the main problem here is the decoding speed by the ST chipset for the ROM chip enable line.. So nothing I can do about that.

So by default the ROM access will have to have a wait state inserted. I will however see if I can tweak the firmware so this can be turned off, some people may get lucky and it may be stable for them.. But obviously I'm going to have to program these with a wait state as the default. I will try to do this with a jumper wire on the back of the GAL... For example wired to 5V is wait states enable, and wired to 0V is wait states disabled.

Once I have created the new firmware (assuming it can be done) I will revisit the 40MHz on this current board...
Would this be another area where a future FPGA-based solution could overcome the limitation of the original chipsets? Not much help right now, but if we have a list of potential improvements to go on the future upgrades then it's all up for discussion.

Also, did I see another post where you considered loading the ROM into fast SRAM to get around some of these limitation?
Or has my brain switched off for the weekend? :lol: :roll:
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

JezC wrote: Fri Nov 09, 2018 2:26 pm Would this be another area where a future FPGA-based solution could overcome the limitation of the original chipsets? Not much help right now, but if we have a list of potential improvements to go on the future upgrades then it's all up for discussion.
If it had its own PLD to do the decoding then it would save something like 10ns... But that isn't something I am going to do with this booster, it would otherwise make the simple design larger and more complicated to gain a few extra MHz... Plus I am not doing any more STE boosters after this one anyway. https://www.exxosforum.co.uk/forum/viewt ... =20&t=1182

JezC wrote: Fri Nov 09, 2018 2:26 pm Also, did I see another post where you considered loading the ROM into fast SRAM to get around some of these limitation?
Or has my brain switched off for the weekend? :lol: :roll:
That was probably in the next gen booster (SEC BOOSTER) where I actually have the same problem that ROM isn't fast enough... So I was considering copying ROM into its own fast RAM block on power up... So all ROM access is done from the fast ram not the actual ROM chip itself.
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by JezC »

exxos wrote: Fri Nov 09, 2018 2:32 pm If it had its own PLD to do the decoding then it would save something like 10ns... But that isn't something I am going to do with this booster, it would otherwise make the simple design larger and more complicated to gain a few extra MHz... Plus I am not doing any more STE boosters after this one anyway. https://www.exxosforum.co.uk/forum/viewt ... =20&t=1182
Yes, I'm fully aware of (and understand) the extra problems with STE/Falcon etc. - just keen to try & help if/when I can to help get the STF remake & successors up to a point to exceed their performance.
exxos wrote: Fri Nov 09, 2018 2:32 pm That was probably in the next gen booster (SEC BOOSTER) where I actually have the same problem that ROM isn't fast enough... So I was considering copying ROM into its own fast RAM block on power up... So all ROM access is done from the fast ram not the actual ROM chip itself.
Sounds like I'd remembered at least some of it correctly then...I'm guessing that the future booster plug-ins for STF remake etc. will be faster CPU with fast memories on-board for the s/w that can use it.
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Re: STE V1.5 32MHz BOOSTER - STATUS

Post by exxos »

JezC wrote: Fri Nov 09, 2018 2:41 pm Sounds like I'd remembered at least some of it correctly then...I'm guessing that the future booster plug-ins for STF remake etc. will be faster CPU with fast memories on-board for the s/w that can use it.
The SEC booster is being prototyped on the STFM, so there will be boosters for that machine... It will take over from the V2.2 booster.. it will also double up for the STF remake booster. The next STF board will have a DIP CPU socket to insert boosters made for the STFM.
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