CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

[exxos]

62 passes so far

I did some quick calculations...

50mhz 20ns x 2 = 40ns (crashes)
40Mhz 25ns x 2 = 50ns (crashes)
50mhz 20ns x 3 = 60ns (OK so far)

does anyone find it coincidental that the ROM access time is 55ns....

[Icky]

62 passes so far

I did some quick calculations...

50mhz 20ns x 2 = 40ns (crashes)
40Mhz 25ns x 2 = 50ns (crashes)
50mhz 20ns x 3 = 60ns (OK so far)

does anyone find it coincidental that the ROM access time is 55ns....

So what is the fastest access time for ROM that will work with the ST?

[exxos]

So what is the fastest access time for ROM that will work with the ST?

The problem is, there is no ROM faster than 55ns... The CPU can 40ns at 50MHz... but they don't exist At least not in OTP 5V stuff.. maybe 3.3V or flash, but not looked in a long time. But a bit irrelevant as I have to use 5V OTP currently anyway.

[Icky]

So what is the fastest access time for ROM that will work with the ST?

The problem is, there is no ROM faster than 55ns... The CPU can 40ns at 50MHz... but they don't exist At least not in OTP 5V stuff.. maybe 3.3V or flash, but not looked in a long time. But a bit irrelevant as I have to use 5V OTP currently anyway.

- Another ceiling reached.

[exxos]

- Another ceiling reached.

Yep. I cannot remember what the speed of the flash chips were which we plotting with even now...

I have also plotted copying the ROM over to a small block of 10ns RAM on power up a while ago..But again its another project..

[Icky]

- Another ceiling reached.

Yep. I cannot remember what the speed of the flash chips were which we plotting with even now...

I have also plotted copying the ROM over to a small block of 10ns RAM on power up a while ago..But again its another project..

I think the flash chips we were looking at for the Flash Clock Dev board could go to down to 45ns

CORRECTION: the 3V versions of the chips go down to 45ns the 5V versions 55ns.

[exxos]

I think the flash chips we were looking at for the Flash Clock Dev board could go to down to 45ns

CORRECTION: the 3V versions of the chips go down to 45ns the 5V versions 55ns.

40ns would equal 50MHz CPU.. I mean if we pushed higher speeds such as 55MHz, then 36ns.. of course PLD delays add a bit to it as well, so would really need 30ns maximum to make it work.. only really possible with some SRAM and copy ROM to it on boot.

[exxos]

Finally have 5 seconds to do something with this again

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it's working out where I got up to with all this from months ago..

The first thing I noticed was the "slow" 267% ROM speed. Normally on the STE at 32 MHz it comes out at 309%...

Reading the notes in the PLD code and looking back in this thread...

https://www.exxosforum.co.uk/forum/viewt ... 440#p23419

It seems it was a speed limit on the ROM itself. Where I had to drop the speed fractionally in order for it to be stable I will start playing around with this again and re-evaluate, I also need to check the blitter operation again.

One thing which is still not solved is the switching back to 8MHz. This board can run in that mode, but the problem of switching 50MHz to 8MHz is not simple because everything is out of sync. I have not had chance yet to look into this problem, but currently I want to get some of these boards out to some beta testers to try before I start working on other problems.

[PhilC]

Those results are still looking good though, can't wait to for some real world comparisons with this.

[exxos]

Those results are still looking good though, cant wait to fo some real world comparisons with this.

As it stands, in relation to "text" related things, this is actually running faster than the blitter...

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