CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

[exxos]

3 hours later...

At least making some progress...

ram.jpg

[exxos]

Still at it...

I gave the autorouter 3 layers to route in, nope, couldn't do it... and yet I got this routed manually before with just 1 layer.

1.JPG

[ijor]

Even so, even 50MHz is probably way too fast. Look at it that how fast they cycle is now, basically 20ns.
Even adding fast ram would mean we would need 10ns RAM which is hard to find and incredibly expensive.

I think talked about this previously that I was considering using a small bank of fast ram (10ns) to copy the ROM contents to during start-up. This is because the flash and ROM chips are basically too slow by themselves. So even adding flash is going to slow ROM access down.

Is that a typo? 10ns RAM for a CPU running at 50MHz? Two RAM accesses per clock cycle?

I assume this is "fast ram" not managed by MMU. You could use static ram then. I think 45ns static Ram is fast enough for full speed without wait states. Should be widely available?

[exxos]

Is that a typo? 10ns RAM for a CPU running at 50MHz? Two RAM accesses per clock cycle?

I assume this is "fast ram" not managed by MMU. You could use static ram then. I think 45ns static Ram is fast enough for full speed without wait states. Should be widely available?

45ns SRAM + 10ns PLD delays is about 55ns cycle time. So CPU can run half that (twice as fast) lets just round it to 50ns, so 25ns CPU can run, at 50MHz thats 20ns per cycle (40ns until DTACK) , so basically the SRAM can run at full speed without wait states.

But for the point of RJ's reply, hes talking about Even faster CPU speeds 64MHz etc, would need even faster RAM, I just said 10ns as a arbitrary figure to make the point. it wasn't intended as a actual figure .

[exxos]

Still at it, but gonna have to call it a day soon, fingers hurting from all the clicking :(

Capture.JPG

[exxos]

Got 10 more wires to route, but will have to wait.. need to work out which pins to wire to the PLD first...

But its starting to look like a final PCB now :)

d47ac980e2b8830bc384717cf010e614.png

37127ce4291462831dec7f2f2dc0c358.png

The spec is 50MHz CPU, 50MHz 8MB Fast-RAM, 50MHz 8MB Flash-ROM.

[ijor]

45ns SRAM + 10ns PLD delays is about 55ns cycle time. So CPU can run half that (twice as fast) lets just round it to 50ns, so 25ns CPU can run, at 50MHz thats 20ns per cycle (40ns until DTACK) , so basically the SRAM can run at full speed without wait states.

I see. I didn't know the PLD was that slow. If the PLD takes 10ns then you need something like 40ns or 35ns RAM for a 50MHz CPU. The CPU can run slightly faster than twice the RAM cycle. You have two and a half cycles from S2 to S7. It might be even possible to use an extra half cycle and start addressing the RAM on S1 if it's very important.

So are you going to implement shadow ram for copying the rom to ram?

[exxos]

.So are you going to implement shadow ram for copying the rom to ram?

No point is there.

[ijor]

.So are you going to implement shadow ram for copying the rom to ram?

No point is there.

I thought you said flash rom is not fast enough for 50 MHZ without wait states?

[exxos]

I thought you said flash rom is not fast enough for 50 MHZ without wait states?

listed the spec here.

https://www.exxosforum.co.uk/forum/viewt ... 390#p17713

flash is 45ns, sram is 45ns.