CURRENT PROTOTYPE STATUS (SEC 64MHz 68000)

[exxos]

Finally got 16MHz working just...

rev1.jpg

Got about 100R on the CPU_CLK now.

The 8MHz clock I put back 68R and 1K pull up PLD side.

So now I have 16MHz CPU..

16mhz.jpg

..and 16MHZ CPU & ROM

16mhzrom.jpg

It's clear I am going to have to do a quick buffer board for these lines.. so probably 2 weeks wait for PCB's to arrive.. Will try and design them tonight..

I also now know how painful 8MHz GEM is over 32MHz on the STE :roll: :lol:

[rpineau]

Nice !
:D
RoRo

[rpineau]

One more thing regarding the Atmel CPLD, we used these properties :

PROPERTY ATMEL {JTAG = ON};
PROPERTY ATMEL {LOGIC_DOUBLING = OFF}; /* OFF - little bit faster without blitter */
PROPERTY ATMEL {PREASSIGN keep};
property ATMEL {OUTPUT_FAST ON}; /* OFF - slower by some % */
property ATMEL {POWER_RESET ON};
property ATMEL {PIN_KEEP OFF};
property ATMEL {CASCADE_LOGIC=OFF}; /* OFF - faster by single % */

That's what gave us the best result and was the most stable
RoRo

[exxos]

This is what I am using..

PROPERTY ATMEL {JTAG = ON};
PROPERTY ATMEL {LOGIC_DOUBLING = OFF};
PROPERTY ATMEL {CASCADE_LOGIC = OFF};
PROPERTY ATMEL {PREASSIGN keep};
property ATMEL {OUTPUT_FAST OFF};
property ATMEL {POWER_RESET ON};
property ATMEL {PIN_KEEP OFF};

Will try fast output while its working..

EDIT:
Nope, makes no odds in my design. All scores exactly the same.


Designed a quick buffer board...

sch.jpg

Ordered :)

5b91f4525e52af0c271c291a3c41d2dc.png

[exxos]

I had another thought to diode clamp the input voltage.

Looking at the DB27308 diode by panasonic http://www.mouser.com/ds/2/315/DB27308_BED-219812.pdf

DB2730800L.JPG

Looking at the graphic, we get about 0.3V drop at 10mA. I'm guessing here at 0.5V undershoot and 68R resistor (0.5/68 = 7.35mA) . So 10mA clamp is pretty much worse case. In practice the voltage and current is probably going to be a little less, and the voltage drop (clamp) will be better.

So what I will have is basically this..

clamp.JPG

I'm a little skeptical of the buffer IC curing this problem. It will clean up the signal a lot, though not totally sure if it will filter out the undershoot. So I will try both methods and see which works best.

[exxos]

Just been looking at flash..

Can only see this one really for 5V parallel SST39SF040-55

http://www.mouser.com/ds/2/268/01360A-709051.pdf


While I can add this to the next booster, I would need someone to write software to program it...

Overall I am thinking the original motherboard ROM could be used to boot from and the flash could be programmed that way. A setting in the booster to boot from the motherboard ROM's to flash the booster ROM. Then switch the booster setting to boot from the flash ROM.

The only slight issues here, is how to program the chip. I don't think there is enough free IO space to map a entire ROM :roll:

I was thinking about just using one register as a program register and just using the PLD to count though each address and program it that way, only problem is, while the CPU will set the flash ROM register, the PLD cannot drive the address bus as well, it would need address isolation so the PLD could drive the flash address bus, but isolate from the CPU address bus.. but that would need a huge PLD...

[rpineau]

It's very hard to find 5V 16 bit flash memory (like the "old" 29F800 and equivalent).
The issue with the SST39SF040-55 is that it's a 8 bit one so you need 2 of these which makes the flashing harder.
I haven't found any flash running at 3.3v with 5v compatible input (I didn't spend a lot of time looking either so there might be some).
Rodolphe

[exxos]

It's very hard to find 5V 16 bit flash memory (like the "old" 29F800 and equivalent).
The issue with the SST39SF040-55 is that it's a 8 bit one so you need 2 of these which makes the flashing harder.
I haven't found any flash running at 3.3v with 5v compatible input (I didn't spend a lot of time looking either so there might be some).

Yeah, I am still looking, 8bit 4MB is all I can find in 5V :( There is also the question if it will run at 32MHz since I was really pushing the 4096 in the STE booster. I'm starting to think it might not be a good idea to mix flash and a booster together, at least not with 5V PLD core.

[rpineau]

There is 1MB of "ROM Space" from $00E00000 to $00EFFFFF so you can remap the ROM in a read part (normal 00E00000) for the first 512KB and a write area for the ;st 512MB and use the address decoding to assert the /W pin of the flash only when the write space is accessed in supervisor mode.
Of course 512KB only gives you space for 2 TOS but better than 1 :)
While you re flashing one you need to be running the other one (you can erase block of 2K or 32K and then write them). That's how the MosSTer works.
so no need to run the whole address bus through the CPLD.
Rodolphe

[exxos]

Was that TOS206 space ? That could be a issue if trying to run TOS206 and writing into that area ?

I was more thinking of just using 1 write register to program the ROM, easy to send data to a register, but no way to step the address bus then :-\

Maybe something like allowing write to ROM space, but if the ROM is controlled by the PLD, then the ROM in use could just be disabled, and enable the second ROM bank for write.

So if we had lower and upper ROM bank, we boot on the lower bank, and "write" to the lower bank, but use PLD logic to flip to the upper bank during write and disable the lower bank ROM during write. This way the system would think it is writing to ROM space that is in use, but actually isn't.

I'm just trying to think of ideas how this could be done. I mean if the motherboard ROM is used, then it will always be TOS104 (or TOS102 etc) , boot from that, then remap the flash ROM to $00EFFFFF for writing. At least this way you can't "brick" the booster as you can always boot from motherboard ROM.