Project: HDMI/DVI out for STFM

[JezC]

Ooooh, I really need this for my H4 no2!

Me too - though I already have the DAC and 32MHz xtal for my #2...

[rubber_jonnie]

Ooooh, I really need this for my H4 no2!

Me too - though I already have the DAC and 32MHz xtal for my #2...

I haven't got that far yet, so don't have the DAC or Xtal, or any of the other bits, so I really need one of these!!

[exxos]

Me too - though I already have the DAC and 32MHz xtal for my #2...

H4 #3

[JezC]

I haven't got that far yet, so don't have the DAC or Xtal, or any of the other bits, so I really need one of these!!

Yes, probably would be much less hassle overall to have the HDMI option...though I guess that is a candidate for a future successor to the H4 (along with native IDE support)...

Mind you, given my rate of (lack of) progress , there is every chance the HDMI will be finished before I even start on Mongrel #2

[JezC]

H4 #3

Maybe when I finally manage a lottery win...

[derkom]

I'm really excited about this project. Superb work! I definitely looking forward to availability.

A quick question, for a curious application: Is it feasible to produce custom output resolutions from these boards? I don't mind if it requires field reprogramming of the FPGA to do it. I've got a couple of LCD panels I'd like to play with, but they do not have any scaling hardware, ergo will display native resolution only. I can use an HDMI-to-HDMI scaler for this, but it would certainly be more elegant to do it internally.

[Smonson]

A quick question, for a curious application: Is it feasible to produce custom output resolutions from these boards?

Short answer: yes.

The current state of the working prototype is they output 4 resolutions depending on 2 jumpers: 800x480 (borders plus a more square aspect ratio on a widescreen TV), 720x480 (borders plus a more widescreen aspect ratio on the same TV), 720x400 (I may be misremembering the width on this one, it could be 800. This is intended to be horizontal borders only for a more square aspect ratio) and 640x400 (no borders at all). The Atari's non-border display area is always 640x400 within that rectangle.

The output res can be anything up to 896x501 minus a few pixels/lines for the sync pulse to fit into. That constraint comes from monochrome. If you make it switch output resolutions when changing video modes then you could go up to 1024x626 (minus a bit) for 50Hz.

Do you know the native dimensions of your TV panel(s) by any chance? I have no information about what's common.

[derkom]

Do you know the native dimensions of your TV panel(s) by any chance? I have no information about what's common.

These are old netbook panels. One is 1366x768 and the other 1280x768. So based on what you say, I'm still looking at having to scale externally. I was hoping that it might have been possible to easily double each dimension on the HDMI board, producing 1280x800, and then cross my fingers the panel would display the first 768 lines, acknowledging the fact that I'm going to lose 16 ST lines at the bottom.

It's kind of a "can this work" thing, not a permanent solution, because of those pesky lines at the bottom. I imagine the real solution here is to use a dedicated scaler, although even in that case, I don't know how well 400/480 lines will scale to 768 lines. Would be nice to have some higher PPI panels to play with.

Edit: I suppose the original question was really "do you happen to have a scaling engine already on that FPGA?" and the answer is "Nope!"

[Smonson]

These are old netbook panels. One is 1366x768 and the other 1280x768. So based on what you say, I'm still looking at having to scale externally. I was hoping that it might have been possible to easily double each dimension on the HDMI board, producing 1280x800, and then cross my fingers the panel would display the first 768 lines, acknowledging the fact that I'm going to lose 16 ST lines at the bottom.

In theory you could double it to 1280x800 but I don't think we have a fast enough pixel clock (32MHz). It may be possible to pump it up a little, as it's using a PLL inside the FPGA. It'd need some experimentation. Let's revisit it later in the project.

[derkom]

In theory you could double it to 1280x800 but I don't think we have a fast enough pixel clock (32MHz). It may be possible to pump it up a little, as it's using a PLL inside the FPGA. It'd need some experimentation. Let's revisit it later in the project.

Sure thing. This was (and will be) definitely a "don't put any actual time into this" thing.