
Here is a more detailed view of the 3V3 bus. We are still working on this area so things may change.
The reasoning behind the bus is to future proof designing add-on boards by saving on adding 3V3 to 5V translators onto these boards. In effect an add-on board to the Phoenix platform using 3V3 technology will not require these translators enabling us to fit more onto these boards and use cheaper 3V3 chips.
The 3V3 bus has two 64 DIL sockets which have all the lines in the 68000 placement but at 3V3 levels. In addition there are two pins used by Flashy Clock - CPU Reset and AUX ROM Drive at the top-middle of the socket and further more 8x IO lines at the right hand side of the socket. These lines currently have 3V3 to 5V translators and end up on the IO1-8 jumper the right of the 3V3 bus area. As we identify more lines to add to the bus we will route to these spare line. We expect there to be some spare so if there is any need to send a line down to the sockets it will be available.