TF CD32 Riser Revision 2 Design Complete

[sugar]

Even though I have retarded dreams of parallel and serial and what not I'm really looking forward for this to happen.

[arkadiusz.makarenko]

I assume this is gone forever?

this is all on my github still. just on a branch.

Branch!
<facepalm>

Thank you.

[arkadiusz.makarenko]

@terriblefire

May I ask what was your plan with RTC? I expected to see signals similar to any other edge connectors on small Amiga like for RTC Read and Write.
But to my surprise I couldn't find any? I couldn't even find them internally in CD32 (they exist only in signal glossary?)

The same question about floppy drive emulation. I can see some of signals on edge, but most of them are missing.
Does it mean that some of the functionality of amiga chipset need to be emulated as well?

Do you mind mentoring this, or are you completely feed up with retro hardware (read community)?

[terriblefire]

@terriblefire

May I ask what was your plan with RTC? I expected to see signals similar to any other edge connectors on small Amiga like for RTC Read and Write.
But to my surprise I couldn't find any? I couldn't even find them internally in CD32 (they exist only in signal glossary?)

The same question about floppy drive emulation. I can see some of signals on edge, but most of them are missing.
Does it mean that some of the functionality of amiga chipset need to be emulated as well?

Do you mind mentoring this, or are you completely feed up with retro hardware (read community)?

This would need to be done by emulating the response you get from the amiga clock port and let the CPLD/ARM decide what data to supply. So the CPLD would need to decode the clockport address and the ARM would feed the data.

From Steady's website...

Code: Select all

$D80000 to $D8FFFF  64 KB SPARE chip select (selected by SPARE_CS)
    (The area of memory where the clock port resides)
$DC0000 to $DCFFFF  64 KB Real Time Clock(RTC) (selected by RTC_CS)

The region of $DC0000 to $DCFFFF is used by an accelerator card that has a built in clock as the RTC_CS signal goes to the A1200 CPU connecotr and can not be used if you have a clock, simple really!

Address lines A2, A3, A4 and A5 only are available. You can only access D16-D23 as well so this yields the following accessible addresses,

$D80001
$D80005
$D80009
$D8000D
$D80011
$D80015
$D80019
$D8001D
$D80021
$D80025
$D80029
$D8002D
$D80031
$D80035
$D80039
$D8003D

Why are the addresses odd?

To read/write to these addresses you need to perform word read/writes under the 68000 architecture.

If you look at those addresses with DiagROM on an amiga with a RTC clock (A1200) you'll see what needs returned. I think you can also get the datasheet for one of the RTC clocks commonly used. Basically you need to decode those addresses and put the data on D31-D24 and assert DSACK0, A real clockport would put the data on D23-16 and assert DSACK1. The CPU get the data the same in either case.

[arkadiusz.makarenko]

@terriblefire

May I ask what was your plan with RTC? I expected to see signals similar to any other edge connectors on small Amiga like for RTC Read and Write.
But to my surprise I couldn't find any? I couldn't even find them internally in CD32 (they exist only in signal glossary?)

The same question about floppy drive emulation. I can see some of signals on edge, but most of them are missing.
Does it mean that some of the functionality of amiga chipset need to be emulated as well?

Do you mind mentoring this, or are you completely feed up with retro hardware (read community)?

This would need to be done by emulating the response you get from the amiga clock port and let the CPLD/ARM decide what data to supply. So the CPLD would need to decode the clockport address and the ARM would feed the data.

From Steady's website...

Code: Select all

$D80000 to $D8FFFF  64 KB SPARE chip select (selected by SPARE_CS)
    (The area of memory where the clock port resides)
$DC0000 to $DCFFFF  64 KB Real Time Clock(RTC) (selected by RTC_CS)

The region of $DC0000 to $DCFFFF is used by an accelerator card that has a built in clock as the RTC_CS signal goes to the A1200 CPU connecotr and can not be used if you have a clock, simple really!

Address lines A2, A3, A4 and A5 only are available. You can only access D16-D23 as well so this yields the following accessible addresses,

$D80001
$D80005
$D80009
$D8000D
$D80011
$D80015
$D80019
$D8001D
$D80021
$D80025
$D80029
$D8002D
$D80031
$D80035
$D80039
$D8003D

Why are the addresses odd?

To read/write to these addresses you need to perform word read/writes under the 68000 architecture.

If you look at those addresses with DiagROM on an amiga with a RTC clock (A1200) you'll see what needs returned. I think you can also get the datasheet for one of the RTC clocks commonly used. Basically you need to decode those addresses and put the data on D31-D24 and assert DSACK0, A real clockport would put the data on D23-16 and assert DSACK1. The CPU get the data the same in either case.

Diagrom! Obviously.
It is just few adress lines, so I can use cheap logic analyser to see what is happening.

I will have a look if stm32 will be able to respond quickly enough (on its own?). That what I found if there is no hardware interface, then on EXTI it takes forever.

[terriblefire]

You should be able to get an ARM to respond to an interrupt inside 1uS. Whole chip was designed to do this even since the ARM1. Something must be wrong.

IntroToCortex-M3.pdf

This says you should be able to get 24 cycles latency.

[arkadiusz.makarenko]

You should be able to get an ARM to respond to an interrupt inside 1uS. Whole chip was designed to do this even since the ARM1. Something must be wrong.

IntroToCortex-M3.pdf

This says you should be able to get 24 cycles latency.

That is what I seen just below 1uS.
I just assumed that it is too slow.

[terriblefire]

Thats the same time it takes the CIA to respond so i think its fine.

This is even true on the CD32. The "CIA" addresses do not respond for 900ns. I think this is so that things that use those ports for timing still get the same results.

[arkadiusz.makarenko]

Thats the same time it takes the CIA to respond so i think its fine.

This is even true on the CD32. The "CIA" addresses do not respond for 900ns. I think this is so that things that use those ports for timing still get the same results.

Hi

I have some more questions (let me know when you are fed up, please)

I have following dilemma.
I am looking at RTC chips, and implementing this should not be that difficult, my issue is that for me it looks like I was missing some address lines on ARM.

Code: Select all

A1200 clock port pin         /A1200 Address           /RTC address      	 /cd32 riser
30                                     /A2                            /RTC_A0             /ARM A2
29                                     /A3                            /RTC_A1             /ARM missing?
28                                     /A4                            /RTC_A2             /ARM 4
27                                     /A5                            /RTC_A3             /ARM missing

I can see following ones A0, A1, A2 and A4

What can't I see here?


RTC chip address/data table

[terriblefire]

The solution to this is to assign one of the INTSIG wires to A5 in the CPLD.

assign INTSIG[x] = A[5]; etc.

This is why i have spare lines for. :)