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MEGA ST BLITTER PATCH - Discussion thread

General discussions or ideas about hardware.
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exxos
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Re: MEGA ST BLITTER PATCH

Post by exxos »

ijor wrote: Tue Oct 04, 2022 8:32 pm This is a about a (slightly) different functional timing. It shouldn't be directly related to analog issues such as spike, noise, overshoot, etc. But it is perfectly possible that there is some coincidence. None of the schematics reflect this different timing.
Thanks. Though wouldn't the blitter patch screw the timings up there somewhere ?

Difficult to surmise that is going on there. One point it seems the differences between national and SGS blitters. But then another post says they are all the same. So was there any definitive results to the testing ?

I can try the blitter's in my H5 if it helps and you upload the program here for me.
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Re: MEGA ST BLITTER PATCH

Post by ijor »

exxos wrote: Tue Oct 04, 2022 8:54 pm Thanks. Though wouldn't the blitter patch screw the timings up there somewhere ?
I don't see how those changes would affect any timing. That logic affects only the output enable of the data bus. No relation with any control logic or synchronous timing. It will probably delay the switching of the data bus by a few nanoseconds, that's all.
Difficult to surmise that is going on there. One point it seems the differences between national and SGS blitters. But then another post says they are all the same. So was there any definitive results to the testing ?
Yeah, it is hard to make and definitive conclusion without more testing. But seems that SGS Blitters are slightly different, and it is probably the oldest designed version (regardless of actual manufacturing date of the specific chip).

The schematics do mention changes in relation to "some" older version. But it is unknown if that older version refers to a prototype or to a chip revision that was actually shipped.
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Re: MEGA ST BLITTER PATCH

Post by exxos »

ijor wrote: Wed Oct 05, 2022 2:45 am I don't see how those changes would affect any timing. That logic affects only the output enable of the data bus. No relation with any control logic or synchronous timing. It will probably delay the switching of the data bus by a few nanoseconds, that's all
I'm talking about the patch PCB. It's clocked by the 8mhz CPU clock, so there will be a clock delay added.
ijor wrote: Wed Oct 05, 2022 2:45 am Yeah, it is hard to make and definitive conclusion without more testing. But seems that SGS Blitters are slightly different, and it is probably the oldest designed version (regardless of actual manufacturing date of the specific chip).
Send me your program, I will test the blitters I have here. I've got all sorts.
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Re: MEGA ST BLITTER PATCH

Post by atari030 »

Without drifting too far down river. How does the MegaSTE differ blitter wise? I've noticed (with some disappointment) that demo's like Sea of Colour will not work on MegaSTE's. DHS's blurb mention something about timing.
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Re: MEGA ST BLITTER PATCH

Post by Badwolf »

exxos wrote: Tue Oct 04, 2022 8:54 pm Thanks. Though wouldn't the blitter patch screw the timings up there somewhere ?
If it's simply a one clock delay of BGK from motherboard to CPU (as the diagram above suggests) then there won't be any functional delay as the CPU has already relinquished the bus and the blitter has already asserted BGK.

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Re: MEGA ST BLITTER PATCH

Post by sporniket »

atari030 wrote: Wed Oct 05, 2022 12:29 pm Without drifting too far down river. How does the MegaSTE differ blitter wise? I've noticed (with some disappointment) that demo's like Sea of Colour will not work on MegaSTE's. DHS's blurb mention something about timing.
Maybe the MegaSTE has the blitter already combined in the MCU ? I know the STe can have external blitter with earlier MCU that have not that.
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Re: MEGA ST BLITTER PATCH

Post by ijor »

exxos wrote: Wed Oct 05, 2022 9:35 am I'm talking about the patch PCB. It's clocked by the 8mhz CPU clock, so there will be a clock delay added.
Ah, I misunderstood, sorry.

It shouldn't affect the normal timing of a Blitter operation because the 'LS74 patch delays only the deassertion of BGACK. BGACK assertion (falling edge) is not delayed, not for a whole cycle, because it is connected both to the DATA and CLR inputs of the 'LS74 flip flop. So a low is propagated asynchronously by the 'LS74, only a high is propagated synchronously.

I would need to double check if this might alter the timing of the CPU taking back bus control. But in anycase it shouldn't affect the current blit, which is what my program tests.

It might also affect the timing of the DMA daisy chain, when both Blitter and GLUE are competing for the bus. Your tech note mentions something about the SLM804 laser printer. Do you have any more details about that?
Send me your program, I will test the blitters I have here. I've got all sorts.
Here it is:
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BLITTST.zip
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http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
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Re: MEGA ST BLITTER PATCH

Post by exxos »

ijor wrote: Wed Oct 05, 2022 2:09 pm Your tech note mentions something about the SLM804 laser printer. Do you have any more details about that?
Afraid not. I think someone sent me the patch article and was in French, hence the bad translation.

Will give your program a go when I get back home later tonight.
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Re: MEGA ST BLITTER PATCH

Post by ijor »

exxos wrote: Wed Oct 05, 2022 2:57 pm Afraid not. I think someone sent me the patch article and was in French, hence the bad translation.
I see. Btw, while the 'LS74 patch itself shouldn't affect the timing of the test, it is still possible that there is some relation. It is possible that the patch is needed precisely in those Blitter chips that have the different timing.
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Re: MEGA ST BLITTER PATCH

Post by exxos »

@ijor These are what I found so far. All show 0040. I've not found and pre 1988 blitters yet :(

IMG_0074.JPG
IMG_0074.JPG (292.75 KiB) Viewed 1752 times

The blitter which isn't very clear is 8824.
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