TF360 Status

[8 Bit Dreams]

I think it will, if You remove FPU disabling routine, just like EC does on stock 4000D without patched roms..

[alenppc]

Not very well and probably only with caches off. Without the MMU you cannot set the cachability of memory regions.

Thats absolutely correct, most programs expect MMU (and FPU) as soon as 060 CPU is detected

Regardless of what software expects, some Apollo 1260 cards were shipped in EC versions in the 90s priced at less than the full 060 versions. I still have some magazine review articles about those somewhere

[terriblefire]

Regardless of what software expects, some Apollo 1260 cards were shipped in EC versions in the 90s priced at less than the full 060 versions. I still have some magazine review articles about those somewhere

Its maybe the wrong topic for this but its nothing to do with software. If you have an EC version version your chipset, chipram and rom will all be cached and there is nothing that can be done in hardware to prevent it.

[xyzzy76]

You should be able to use the transparent translation register(s) to disable cache in the lower 24 bit space.

The 68040 contains two registers to give data space a default
mapping without the need of a Memory Management Unit (MMU). On an
Amiga with a 68040, Exec uses one of these registers to map the low
24-bits of the Amiga's address space (the Zorro II range,
$00000000-$00FFFFFFFF) as non-cachable and serialized1 .

The Amiga uses the second register to map the remaining memory
($01000000-$FFFFFFFF) as cachable and non-serialized. Because of its
mapping, any RAM in this region will yield considerably higher
performance than RAM in Zorro II space.

http://amigadev.elowar.com/read/ADCD_2. ... e0161.html

1.1.2.1 ADDRESS TRANSLATION DIFFERENCES. Although the MC68EC060 has no
paged MMU, the four transparent translation registers (ITT0, ITT1, DTT0, and DTT1) and
the default transparent translation (defined by certain bits in the translation control register
(TCR)) operate normally and can still be used to assign cache modes and supervisor and
write protection for given address ranges. All addresses can be mapped by the four transparent translation registers (TTRs) and the default transparent translation.

[terriblefire]

Ok so i'd need to do that in the startup rom... does anyone have the rom (sitts at 0xf00000) from one of those boards with an EC cpu.

[alenppc]

In the meantime, I am trying the various CPU masks (full versions). They all seem to run without issue... Quake demo runs fine, no crashes, everything seems nice and stable so far.

I am running on a rev 6 now. time to try 75 mhz?

My only issue so far is that the voltage regulator is so hot you can insta-fry an egg on it. You can't touch it at all. If I went to one with more amps, would it run cooler?

[terriblefire]

Yeah if you have a 150Mhz crystal it should work :)

I'm using a tbtorro switched mode psu module now. Seems to take all the heat out of it.

[8 Bit Dreams]

Guy's try traco power TSR 2-2433

Mouser number: 495-TSR2-2433
2A and no heat at all...

[terriblefire]

Guy's try traco power TSR 2-2433

Mouser number: 495-TSR2-2433
2A and no heat at all...

That looks good. Im just slightly concerned about the size of it. i.e. will it be too big to let a user install a TF360.

[alenppc]

No luck at 75 Mhz.

The rev1 CPU yellow-screens. One of the two rev6 CPUs crashes immediately after boot. The other makes it to workbench but then it freezes immediately.