So that didn't work.

47pF now removed.
I guess its possible while the ringing can be solved, maybe the slight delay it causes on the SDMA clock causes it to become unstable
If its stable without the 47pF, I may see if I can find my PLL prototype board, as that compensates for the SDMA clock delay. Then I could retry the 47pF to see if clock sync is a factor or not...
and its locked up again
I will connect the SDMA clock to the combel clock then it will be a few ns ahead of the combel clock, but by the time its got to the SDMA it ends up 4ns slower anyway, but 2 buffers less it should basically all be in sync then...
EDIT:
Nope

So will have to put back the V3 and rerun tests again as that one uses inverters not buffers.. This means combel is then out of sync with everything else..
EDIT2:
Nope V3 isn't working again now.. I don't get it. Was working last night.

Maybe I am barking up the wrong tree and there's some other odd fault on this board somewhere.
EDIT3:
I've removed the 62R from the SDMA line as that wasn't there yesterday.. running tests again now.. The SDMA clock doesn't look great. High of 3.80V or thereabouts.
I did design a V6 clock patch a few months ago. That one is a mix between V3 and V4. But it has the option for inverting and noninverting .
Assuming this is a SDMA clock fault, the V6 would up the voltage to the SDMA clock.. If it works worse.. then maybe the SDMA doesn't like a higher voltage...
Will have to see how V3 works as another baseline test now.
I suppose - I could hack on a ~6V regulator on the V3 to up the voltage output a bit to see if that helps or not first...