Sidequest: VGA scan doubler

[Smonson]

Might indeed be a bug, but not necessarily so. It might as well be just a timing issue.

At least you're adding a mux into a (probably already timing critical) combinational circuit that might cause that bit of delay that makes the signal missing the next register (probably an I/O cell?) in time (Lattice chips aren't especially known for outstanding performance).

Does that toolchain come with a timing analyzer?

Yeah, it produces a timing report with the propagation delay of various nets, but also I have given it a global timing budget of 32MHz (31nS) which it is easily meeting. The slowest net in the design is about 8nS. So it should be able to route it with no trouble. I'm only using 30% of the chip so there's also plenty of room to manoeuver.

It's possible that it's trying to tell me something that I don't understand among its 10K lines of output - it's a weirdness of this software that it spams the terminal, but does not stop for errors, even critical verilog syntax errors, which is slightly concerning. That's why I also use Icarus to simulate the design because it actually tells you if there's a mistake :)

[ijor]

Since the Lattice software is all self-contained, I'm sure it'll be fine to run it on Windows, just nothing else in my GNU-based toolbhain will work. So I have the pain of copying the source code on there, compiling it, then rebooting back into Linux to program the chip. Good for confirming whether it could fix the problem but not good for actual working, although if I use 2 laptops simultaneously I could probably live with it.

Again, use a Virtual Machine to run Windows on Linux. That is not Wine, a VM can run full Windows. You then get Linux and Windows running on the same PC at the same time. No need to reboot, you can even easily transfer or share files between both systems. I do this all the time.

It's possible that it's trying to tell me something that I don't understand among its 10K lines of output - it's a weirdness of this software that it spams the terminal, but does not stop for errors, even critical verilog syntax errors, which is slightly concerning. That's why I also use Icarus to simulate the design because it actually tells you if there's a mistake.

This is not good. You have to check every single message because there might be a critical warning. Simulation is good, but simulation can't catch all the possible issues.

If the compiler issues too many warning and it doesn't have a message suppress manager, then that's enough reason to avoid that compiler. Good compilers have some kind of message manager precisely for this purpose.

[b_squared]

It is impossible to work with tools that you don't trust. Might be the compiler or might be not, but you have to use known good, reliable, tools.

I understand from what you are saying that you usually develop on Linux and compiling on Windows might be a bit problematic for you. Use a VM to run Windows (virtualized on Linux) in the worst case.

Since the Lattice software is all self-contained, I'm sure it'll be fine to run it on Windows, just nothing else in my GNU-based toolbhain will work. So I have the pain of copying the source code on there, compiling it, then rebooting back into Linux to program the chip. Good for confirming whether it could fix the problem but not good for actual working, although if I use 2 laptops simultaneously I could probably live with it.

For whatever it's worth, I was running Max+Plus II under Wine successfully about 20 years ago to do my university projects. It's absolutely worth a try.