Flashy Clock - Yet another DEV board

[exxos]

Finally making some progress!

All the flash routines are being moved from the main menu into this new sub menu. I couldn't make the window any taller for all the options

This is the menu for dealing with all the flash erasing and programming. So you just simply select the bank number, and you can only raise or program, and that is it!

The "VALID" text means the header is correct ($602E). If the header is anything else, it will report "ERROR". the program routine will not allow you to program the flash if these bites are backwards, in which case you will need to byte swap the file. Currently you shall be able to download the ROM images and flash them directly without having to byte swap them. Theoretically nobody should ever get "ERROR" in this menu. If the bank is blank, it will say "BLANK FFFF".

Thanks to the EMUTOS guys for adding the version numbers into EMUTOS, we can now read the actual version number. Currently at the time of typing there is no official release which supports this numbering as yet, but if no version number is available, it will just simply state "EMUTOS". basically this will show the versions 9.12 and below (all older versions of EMUTOS) .

If you are not bothered about the technicals, skip reading the below bit

STAT-REG is basically a debugging output more than anything. This register is a little complicated to explain...

xxABCDEF 11111GHI

A = READS ROM_DIS PHYSICAL JUMPER
B = PLD REGISTER OF FLASH SELECT 2 READ ONLY
C = PLD REGISTER OF FLASH SELECT 1 READ ONLY

D = PLD INTERNAL STATUS REGISTER OF ROM_DIS
E = PLD REGISTER OF FLASH SELECT 2 STORED IN NVRAM
F = PLD REGISTER OF FLASH SELECT 1 STORED IN NVRAM

G = ROM_DIS AS STORED IN NVRAM
H = BOOT FLASH BANK SELECT 2
I = BOOT FLASH BANK SELECT 1

x = don't care

The reason for the multiple ROM_DIS registers is because we have a physical jump on the board which can set ROM_DIS HI. also this can be set via software where the value is also stored in NVRAM. Theoretically bits G & D should always be equal.

H & I registers (I am was working on this part of the software now) are the flash bank select registers which I am calling the "BOOT ROM". these are the registers which are stored in NVRAM. so if you select bank 1, this value is set and stored in NVRAM and also restored when you power up your machine.

E & F registers are also flash bank select lines, but these are "temporary" lines which override the "BOOT ROM" registers during programming. as said earlier, there is not enough address space to map the entire ROM banks in full, so a register is used to allow the flash address lines to be changed automatically in the PLD. Whichever bank is selected will be presented in address $E40000, which is also the area used to actually program the flash.

Another way to look at the registers is that the low byte is a mirror of NVRAM 7F register, and the high byte the status of the internal PLD registers.

IMG_4750.JPG (85.7 KiB) Viewed 3893 times

[czietz]

Small detail, in case you want to support TOS 1.00 as well: That version does not start with $602E.

[exxos]

Small detail, in case you want to support TOS 1.00 as well: That version does not start with $602E.

Thanks.. never gave anything below TOS1.04 a thought.

[exxos]

The boot bank menu is finally working

This may be a little tricky to understand as it apparently has conflicting messages.. On the left it says it is running from MB ROM, but on the right it says flash bank for is selected... Actually both for these are true..

The condition is that if the motherboard ROM is selected either by register 7F (in NVRAM) or by the physical jumper on the PCB, the machine will boot from the motherboard ROM. This condition is essentially a bypass condition for the flash banks. The flash banks themselves are still actually selected as shown just not currently in use because it is running from the motherboard ROMs. Or if you prefer, it is just simply stating what the flash bank registers are doing in register 7F.

So in the case of the below image, bank 4 is selected, and is stored in 7F (NVRAM) Machine is actually currently running from MB ROM because bit3 in register 7F is set HI.

The stat-reg bit 3 is low, because the physical motherboard jumper is turned off. If the jumper on the board was turned on, that it would go high, and regardless of bit 3 in register 7F, the motherboard ROM will be used. So basically the physical jump on the board is a override for bit 3 in register 7F. The reason for this apparent complexity is that this is going to be called the "unbrick mode".

The unbrick mode is basically if someone really manages to screw up the registers somehow causing the board not to boot any longer, or basically the board's new and has no flash banks programmed yet. So the unbrick mode is used to forcefully boot from motherboard ROMs so you can program the flash banks and set up the registers etc.

The good thing about all this is that you can still use the motherboard ROMs conjunction with the flash banks. Basically this would ordinarily give you 5 effective ROM banks you can use. Of course if you have a DUALTOS board you would in effect have 6 banks. Though the motherboard ROMs are not currently controlled by the PLD.. *yet*.

In version 5 of this board which Icky is routing up currently, we will have a auxiliary output to control one of my dualtos boards as mentioned a few days ago. This basically means you could have a dualTOS 104 & 206 in the motherboard, and still have the 4 flash banks free to use. But these are really things for another day anyway. Version 5 will also have its own hardware reset circuit. Currently when you change banks (depending exactly what mode you are in and using etc) but you basically end up with the machine crashing. Currently the software will just inform you to press the reset button and then it will reboot in the bank you just selected. Version 5 will automatically reset the machine for you. I also have other features and ideas which will be born into version 6 most likely.

So overall this project is basically(almost) DONE! I think @Icky May have a couple more of the current V3 PCB's. so hopefully after Christmas we can build up a couple more so people can test them out. Hopefully once Icky has a board with a 1508 on it, he can do a video on it and show off all the features and stuff it can do.

Hopefully after Christmas I will get my alt-ram boards back as these plug into flashy V3 anyway. It should not take long to get the alt-ram up and working on it.

IMG_4751.JPG (75.72 KiB) Viewed 3875 times

[exxos]

Another small thought.. When using TOS206, I could maybe fake the jumpers on the STE, well the register, to enable 1.44 formatting in the desktop menu.

Also myself and Icky are toying with trying to get this all working with 3.3V stuff as its way cheaper than 5V stuff. The cost of this ultimately could well end up being £150+ mark otherwise. Though the addition of level translators on this design will likely result in us using a 6 layer board, which is really expensive. But as 3.3V stuff is a lot cheaper, like the SRAM chips are £20 a pop and there's 4 of them! We could do the same job in a single 3.3V SRAM for just £20. So overall it would save a lot of costs.

I also am half thinking of future H4 boards to have a integrated 3.3V bus on maybe the 3 right side 68K sockets. With FPGA stuff looming, we really need a proper 3.3V bus , or at least starting to implement it anyway.

[exxos]

Does anyone know the register the STE has those jumpers at to enable the 1.44 floppy format option in GEM ? I can't seem to find it anywhere

[Icky]

Does anyone know the register the STE has those jumpers at to enable the 1.44 floppy format option in GEM ? I can't seem to find it anywhere

A quick search and I could only find info in the Cookie Jar related to floppy format

Code: Select all

                                   Cookie Jar
                            Atari "Official" Cookies
Cookie  Description
-------+----------------------------------------------------------------------
_FDC   | Floppy Drive Controller                              BIT 25 24 . 23-0
       | Floppy Format                                             |  |      |
       | 00 - DD (Normal floppy interface) ------------------------+--+      |
       | 01 - HD (1.44 MB with 3.5") ------------------------------+--+      |
       | 10 - ED (2.88 MB with 3.5") ------------------------------+--'      |
       | Controller ID                                                       |
       | 0 - No information available                                        |
       | 'ATC' - Fully compatible interface built in a way that -------------+
       |         behaves like part of the system.                            |
       | 'DP1' - "DreamPark Development", all ID's beginning with -----------'
       |         "DP" are reserved for Dreampark.
-------+----------------------------------------------------------------------

[exxos]

A quick search and I could only find info in the Cookie Jar related to floppy format

No idea what the cookies for

I cannot even find anywhere which even mentions enabling HDD format from the desktop

EDIT:

Trying to find signal in the MCU schematic, see if I can work it out that way..

EDIT2: Nope, just doesn't seem to be in there. I did find a site which claimed the cookie needs to be set to enable the desktop menu.. Though not sure how that would translate from the jumper on the STE to a cookie though.

[exxos]

So as normal exxos has jumped a rail and after talking to @Icky earlier, decided to put V5 on hold and go for the V6... basically half because the chips in 5V are expensive, but also I think there is little point in spending time designing a version 5 when it is already obsolete for the version 6.

As discussed previously, this will have a bank of IO level shifters on the bottom of the board to interface to the 3.3V stuff. But also,SRAM is a lot cheaper & smaller in 3.3V.. Because the flash can be done in a single chip, I am hoping this will free up enough room to actually solder the SRAM to flashy instead of having a separate PCB with the SRAM on. Those PCBs were expensive to produce because of the very tight tolerances on them.. Technically I'm writing off those boards, but they would still have to be used with the SEC booster anyway.

As always, I am also thinking of the version after that as well But likely there would be 2 versions of V6 which would be produced with and without the SRAM.. If people do not want the alt-ram then they can just buy the cheaper version without it.

I was also looking at higher capacity flash chips.. We could look into actually having 8 flash banks, but I really do not know why anyone would need so many banks anyway? It would be pretty cool if they could be used as some type of flash drive, But I have no idea if that is possible or how to do it.

I am also looking into getting the remaining pcbs (about 6) of the version 3 boards built. Basically myself and Icky need one which works properly. But any remaining boards I hope will be up for grabs in the near future.

[JezC]

If you need any help with the s/w for the Flash then I'd be happy to help if you need it.

It's probably over 20 years since I did any GEM programming but I work with reading/writing various Flash memory devices (both parallel and serial) pretty much every day at work (mostly in C) so I might be able to help lighten the load a bit...

Plus, it's either something like that or a much less productive diversion over the next few weeks until my H4 boards arrive...unless I finally pull my finger out & start fixing all my Ataris & peripherals!

Would also be nice if I can contribute in any way to the ongoing advancement of the ST remakes