ST-IDE-ROM Dev Board v1 - BETA Testers

[exxos]

Ok, I found an anomaly I believe. According to the schematic IORDY is connected from pin 27 on the IDE connector through a 100 ohm resister to pin 6 on the sip to pin 62 on the plcc. I'm missing the connection from pin 62 on the plcc to pin 6 on the sip. It appears to be mixed up with the Icky specified fixes. Is the schematic correct in this area? :?: :?: :?:

ah nope, the schematic seems to be "before" the wire mod was done...

Basically pin 62 and 64 get swapped on the PLD..

IORDY actually goes to pin 64 of the PLD (not 62 as in the schematic)

Then the TCK signal which is on the schematic as pin 64, is actually on pin 62 after the wire mod.. ..

sorry about that, the schematics I don't think were updated as we moved onto the next version...

[Icky]

sorry about that, the schematics I don't think were updated as we moved onto the next version...

I have an updated schematic. This schematic is the patched one. The joys of pair designing :)

[PaulJ]

sorry about that, the schematics I don't think were updated as we moved onto the next version...

I have an updated schematic. This schematic is the patched one. The joys of pair designing :)

So does TCK just come out to r3 a 10k resistor to ground and pin 1 off a header?

[exxos]

So does TCK just come out to r3 a 10k resistor to ground and pin 1 off a header?

Yes.

[PaulJ]

sorry about that, the schematics I don't think were updated as we moved onto the next version...

I have an updated schematic. This schematic is the patched one. The joys of pair designing :)

Icky, could you check you fix it up pic in section 2. Your enhanced virtual wire goes to pin 5 of the sip.... not pin 6 which is connected to pin 64 of the plcc (IORDY).. Your virtual wire covers up the actual wire so I can't truly determine where it goes. Am I correct?

[Icky]

I have an updated schematic. This schematic is the patched one. The joys of pair designing :)

Icky, could you check you fix it up pic in section 2. Your enhanced virtual wire goes to pin 5 of the sip.... not pin 6 which is connected to pin 64 of the plcc (IORDY).. Your virtual wire covers up the actual wire so I can't truly determine where it goes. Am I correct?

Checking.....

[Icky]

Icky, could you check you fix it up pic in section 2. Your enhanced virtual wire goes to pin 5 of the sip.... not pin 6 which is connected to pin 64 of the plcc (IORDY).. Your virtual wire covers up the actual wire so I can't truly determine where it goes. Am I correct?

Checking.....

Actual picture of patch. Hope this helps. Don't forget the cut track.

IMG_3590.jpg

[PaulJ]

I'm confused Icky. You have the jumper going to pin 5 of the sip. If you check with an meter pin 27 of the IDE connector goes to pin 6 of the sip through a hundred owns. Pin 1 of the sip which is power is on the top of the picture. Pin 6 is the one with the trace cut to the right of the pin 6???

[PaulJ]

Its pin 5 counted from either end of the sip.

[rubber_jonnie]

Positive progress tonight, ROMs off the test mainboard now, and the 1.04/2.06 ROM fitted to the IDE board. The machine now boots to either TOS dependent on the selector jumper.

Even better, it's the ROM I programmed myself after fixing the PLCCto DIL adapter board last night, so I know the fix to the programmer works properly.

Last thing to do before testing IDE is the select1/2 patch with resistors and caps, just no time tonight. Hopefully get it done Wednesday.