BLITTER RE-CREATION THOUGHTS

[mmx01]

More I look at the timings, more I think PLL should be clocked from external crystal and CLK as signal synced to Atari. This would sync bus events but not impede logic operations. Perhaps that's a dead ally but first impression is that processing is consuming too many cycles. Or fiddle with P_CYCLE_CNT: process.

[mmx01]

Tried to get blitter on 16Mhz clock from MMU pin 5 but it did get messy, division of clock counts in fpga code did not seem to improve anything. I wish I had designed some pads around clock source configuration but yeah...

Thanks to great input from @Icky and a lot of hacking hours not fully understanding ports, port maps and how to pass different signals in vhdl finally some progress! This code provided other insights how to further tune fpga blitter:

https://github.com/gyurco/MiSTery/commi ... 6f252776f7

Still not good though, lines no longer spread over time but top part is distorted. Playing with 32Mhz vs. 64Mhz clocks is not delivering further benefits.

20211214_133834.jpg

Stock code - blitting score in mid-res: time 5.965
New code - blitting score in mid-res: time 6.600

Hmm. not going in the right direction but at least new code is working and not freezing the machine like it did for 2 days ;) Next seems to be waitstates, T_SLICE and CYCLE_CNT. T_SLICE I am feeding 8Mhz and overall clock is 32Mhz I will try to rewrite with raising edge & falling edge. CYCLE_CNT for HOG is 80/40.

[Icky]

Thought I would do the final spin of the Phoenix Sparkalaphobia board now that the dev boards are functioning and its down to the firmware tweaks to complete.

This board is designed to fit directly into a PLCC68 socket as a drop in replacement of an original BLITTER chip.

Of course the most limiting factor now is the FPGA chip shortage.

Screenshot 2022-10-15 at 13.46.00.png

Screenshot 2022-10-15 at 13.47.02.png

Screenshot 2022-10-15 at 13.42.12.png

[Badwolf]

This board is designed to fit directly into a PLCC68 socket as a drop in replacement of an original BLITTER chip.

Looking good. What chips are you using for the level shifting there, BTW?

BW

[Icky]

This board is designed to fit directly into a PLCC68 socket as a drop in replacement of an original BLITTER chip.

Looking good. What chips are you using for the level shifting there, BTW?

BW

GTL2010PW - https://www.ti.com/lit/ds/symlink/sn74gtl2010.pdf

@exxos had done various testing of translators and we have found these to be best suited to our needs. Its also the same ones we use on the H5 boards to provide the 3V3 bus. I cant seem to find the thread on @exxos' experiments.

[Badwolf]

GTL2010PW - https://www.ti.com/lit/ds/symlink/sn74gtl2010.pdf
@exxos had done various testing of translators and we have found these to be best suited to our needs. Its also the same ones we use on the H5 boards to provide the 3V3 bus. I cant seem to find the thread on @exxos' experiments.

Cheers, will have a look at those. My normal ones are only 8 bits wide and are occasionally unobtanium.

BW

[exxos]

@exxos had done various testing of translators and we have found these to be best suited to our needs. Its also the same ones we use on the H5 boards to provide the 3V3 bus. I cant seem to find the thread on @exxos' experiments.

Its all at the start of this thread. Experiments are scattered over several pages.

viewtopic.php?p=9808#p9808

The GTL chips were the only ones I could get to work right. Even Texas versions of the same chip were screwy IIRC.

[Tbs123456]

Is it a 100% blitter replacement?

Where did the name sparkalaphobia(pronounced spark-ala-phobia?) Come from?

[exxos]

Is it a 100% blitter replacement?

Yes. Its a project to offer a alternative to the impossible to find Blitter chips.

Where did the name sparkalaphobia(pronounced spark-ala-phobia?) Come from?

Sparkalaphobia - The fear of Glitter.. Glitter as autocorrect keeps changing Blitter to Glitter :lol: :roll:

[Cyprian]

how to buy that glitter
my ST is waiting for it