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Treating the symptom rather than the cause, but stability greatly improved by a late-in-the-day check for IPL mismatch.
The issue I was seeing repeatedly was that the interrupt acknowledge cycle was often generating a bus error because there was no actual interrupt to acknowledge!
The IRQ system in PiStorm is very opaque and any change to what often appear magic numbers causes it all to fall apart. So I've kind of admitted defeat for now and implemented this check. I still have seen a couple of errors, but things are better.
The big issue is still bus access speed. Unfortunately the gap between bus cycles is too large. One cycle to the next is ~1us whereas on a proper 8MHz 68000 it's ~500ns. Hence I'm seeing 50% speed (the figures above should be 3.7MB/s).
There are two contributory factors to this. Firstly turning on bus (and address) errors costs time. Secondly, the Amiga asserts it data earlier in the cycle meaning PiStorm can normally just abandon the cycle early, meaning the cycle-to-cycle time comes down. We can't on the ST as data is only asserted at the 'correct' time, meaning we have to go through a full three-clock bus cycle.
Of course, turning on the features -- TT-RAM, 020 processor, virtual ROM, mitigates this to some extent on OS-based apps (see below), but the RAM speed still never gets above 57%.
I might have to learn how to do profiling on a multithreaded linux app to know where to go next.
BW
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