Let's build a CTPCI!

[dml]

Thanks, I think that's enough info for me to make a start on it!

[dml]

The DigiKey order arrived already so I guess it's time to order a few PCBs...

[foft]

Wow that was quick, even by Digikey standards!

Crossing my fingers for the build.

[dml]

Wow that was quick, even by Digikey standards!

It was surprisingly quick!

Crossing my fingers for the build.

Thanks.

I do have some more questions meantime...

I don't see a public/shared project for CTPCI on PCBWay (some other Atari stuff there but not this) so presumably I'm uploading the files myself for a quote.

The board size needs to be entered as part of the quote (seems to be 100mm x 64mm?) and the layer count.

Having checked the gerbers in KiCad/gerbview, there are 11 layers - I think some are silkscreen but I'm not completely sure what to enter as the layercount on PCBWay quote page. Any tips welcome before I try to get the order in.

Hmm... actually there seem to be a lot of settings which need specified before uploading the gerbers. Hole sizes, thickness parameters... was hoping those would get extracted from the archive.

[DoG]

Wow that was quick, even by Digikey standards!

It was surprisingly quick!

Crossing my fingers for the build.

Thanks.

I do have some more questions meantime...

I don't see a public/shared project for CTPCI on PCBWay (some other Atari stuff there but not this) so presumably I'm uploading the files myself for a quote.

The board size needs to be entered as part of the quote (seems to be 100mm x 64mm?) and the layer count.

Having checked the gerbers in KiCad/gerbview, there are 11 layers - I think some are silkscreen but I'm not completely sure what to enter as the layercount on PCBWay quote page. Any tips welcome before I try to get the order in.

Hmm... actually there seem to be a lot of settings which need specified before uploading the gerbers. Hole sizes, thickness parameters... was hoping those would get extracted from the archive.

Is it the same if you upload to JLCPCB?

[dml]

Is it the same if you upload to JLCPCB?

It's definitely worth a look. I'll investigate a bit later.

[...time passes...]

So that was worth a try - uploading gerbers is available as a 1st step and it derived most of the settings from the archive. It did detect a 2-layer PCB so hopefully that is correct. I'll need to study the layers properly to be sure of that.

And it works out pretty cheap for 2-layers.

I ticked the 12-layer option on PCBWay and it quoted me $740 for 5 boards so that answers my earlier question I think. The layer choice is for the copper not the total design layers in the gerber...

Anyway I'll spend a bit more time looking at the gerbers, confirm the layer count and get an order placed.

[foft]

The main board is 4 layers and the pci slot board is 2 layers. I thought pcbway detected them all.

[dml]

The main board is 4 layers and the pci slot board is 2 layers. I thought pcbway detected them all.

The autodetect was JLCPCB - but thanks for confirming the real layer count

[dml]

Now things are getting confusing (yay)

Ignoring the PCI slot board for a minute, the main board lists 11 design layers in KiCad gerbview.

On JLCPCB's viewer, it identifies the same 11 design layers and names them all - although in a different order.

1) top silkscreen
2) bottom silkscreen
3) top paste mask layer
4) bottom paste mask layer

These all appear to check out against the layer content.


5) top layer
6) bottom layer

These are the only two layers with tracks


7) bottom solder mask layer
8) bottom paste mask layer
9) vcut
10) drills
11) sk

Not sure what vcut (vias?) or sk are but they don't seem to be track layers.


This is from the CTPCI_aligned_gerbers.zip archive, containing 11 files mapping to the 11 design layers.


So if layers 5/6 are the front/back track layers, what/where are the missing 2 middle layers? Or are the solder paste layers counted here?

Appreciate the help/feedback but I think it's important to have clarification on this in case I'm looking at the wrong materials. Although it does look reasonable.

[dml]

And now I'm studying the front/back layer in gerbview - and I see vias which end in empty space, suggesting there are layers missing.

....

....

Not sure what's going on now but it seems like the zip is missing pieces - or some files have multiple layers that are not detected by KiCad or JLCPCB.

Well this is already fun!